dts: clock: stm32 common: bindings for pllp, pllq, pllr clock sources
This commit introduces bindings that allow socs compatible with the
stm32 common driver to use the pll outputs pll_p, pll_q, pll_r,
to be used as a clock source for peripherals.
These are to be used instead of the, now removed, STM32_SRC_PLLCLK.
Applies to: STM32G0, STM32G4, STM32L4, STM32L5, STM32WB, and STM32WL.
STM32F2, and STM32F4 are not considered: very similar but only very limited
configuration possible. Only I2S(EXTclock,PLL_R), MC01, MCO2,
PLL_Q for 48MHz clock, and PLL_P as PLLCLK.
Doesn't apply to STM32L0, and STM32L1 which only have PLLMUL and PLLDIV.
Doesn't apply to STM32F0, STM32F1, STM32F3 only having a PLLMUL,
and no divider.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
5 files changed
