| commit | 168da2617f25260ad72ac1fdbbb8cd15bcf5bdd9 | [log] [tgz] |
|---|---|---|
| author | Andy Ross <andrew.j.ross@intel.com> | Tue Dec 14 12:48:59 2021 -0800 |
| committer | Anas Nashif <anas.nashif@intel.com> | Wed Jan 05 15:01:45 2022 -0500 |
| tree | dedfb27c7ddfdd57814c08abba5f4421a0dc9127 | |
| parent | 422c2ec0f3c10e4bb3506f172412ae5cd7d99bb5 [diff] |
soc/intel_adsp: Don't depend on XCHAL_EXCM_LEVEL The MP startup code had a hardcoded INTLEVEL field of 5 in the initial value of PS. That's needless, INTLEVEL is a full 4 bit field even if the number of hardware interrupt levels is lower (and in fact 0xf is the documented hardware reset state). Set that instead, so that this code will work with any XEA2 hardware. This also matches the similar code path in boot startup. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>