| commit | 175407c9cc2af6b3417f55df68e7601920b00cce | [log] [tgz] |
|---|---|---|
| author | Naveen Gangadharan <naveeng1001@meta.com> | Mon Oct 07 16:56:33 2024 -0700 |
| committer | Carles Cufí <carles.cufi@nordicsemi.no> | Thu Oct 10 10:07:00 2024 +0200 |
| tree | 9eeae6c6b82a1a2be3ad0068023bf4c596435528 | |
| parent | e48639e460227da0dda74f07069558cf23ef5e92 [diff] |
drivers: i3c: cadence: fix HDR-DDR write failures due to M1 errors Fix M1 errors seen with HDR-DDR writes, M1 errors we seen between CRC and HDR exit sequence. The fix was to set Bit-8 of HDR-DDR CRC TXFIFO word. Signed-off-by: Naveen Gangadharan <naveeng1001@meta.com>