boards: add support for ifx kit_pse84_eval
- add needed board files for kit_pse84_eval board
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
diff --git a/boards/infineon/kit_pse84_eval/Kconfig.kit_pse84_eval b/boards/infineon/kit_pse84_eval/Kconfig.kit_pse84_eval
new file mode 100644
index 0000000..3122e41
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/Kconfig.kit_pse84_eval
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# PSOC E84 Configuration
+
+config BOARD_KIT_PSE84_EVAL
+ select SOC_PSE846GPS2DBZC4A_M33 if BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M33
+ select SOC_PSE846GPS2DBZC4A_M55 if BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M55
diff --git a/boards/infineon/kit_pse84_eval/board.cmake b/boards/infineon/kit_pse84_eval/board.cmake
new file mode 100644
index 0000000..40792b0
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/board.cmake
@@ -0,0 +1,21 @@
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_CPU_CORTEX_M55)
+ # Connect to the second port for CM55 (default port is 3333)
+ board_runner_args(openocd "--gdb-init=target extended-remote :3334")
+endif()
+
+board_runner_args(openocd --no-load --no-targets --no-halt)
+board_runner_args(openocd "--gdb-init=maint flush register-cache")
+board_runner_args(openocd "--gdb-init=tb main")
+board_runner_args(openocd "--gdb-init=continue")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+
+if(CONFIG_CPU_CORTEX_M33 AND CONFIG_TRUSTED_EXECUTION_SECURE)
+ set_property(TARGET runners_yaml_props_target
+ PROPERTY hex_file ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.signed.hex)
+endif()
diff --git a/boards/infineon/kit_pse84_eval/board.yml b/boards/infineon/kit_pse84_eval/board.yml
new file mode 100644
index 0000000..821aeea
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/board.yml
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+ name: kit_pse84_eval
+ full_name: kit_pse84_eval
+ vendor: infineon
+ socs:
+ - name: pse846gps2dbzc4a
diff --git a/boards/infineon/kit_pse84_eval/doc/index.rst b/boards/infineon/kit_pse84_eval/doc/index.rst
new file mode 100644
index 0000000..ffd19ca
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/doc/index.rst
@@ -0,0 +1,143 @@
+.. zephyr:board:: kit_pse84_eval
+
+Overview
+********
+The PSOC™ Edge E84 Evaluation Kit enables applications to use the PSOC™ Edge E84 Series
+Microcontroller (MCU) together with multiple on-board multimedia, Machine Learning (ML),
+and connectivity features including custom MIPI-DSI displays, audio interfaces,
+and AIROC™ Wi-Fi and Bluetooth® combo-based connectivity modules.
+
+The PSOC™ Edge E84 MCUs are based on high-performance Arm® Cortex®-M55 including Helium DSP support,
+an Ethos™-U55 NPU, and a low-power Arm® Cortex®-M33 paired with Infineon's ultra-low power NNLite
+hardware accelerator. They integrate 2.5D graphics accelerators and display interfaces, while
+featuring always-on acoustic activity and wake-word detection, efficient HMI operations, and
+extended battery life.
+
+The evaluation kit carries a PSOC™ Edge E84 MCU on a SODIMM-based detachable SOM board connected to
+the baseboard. The MCU SOM also has 128 MB of QSP| Flash, 1GB of Octal Flash, 128MB of Octal RAM,
+PSOC™ 4000T as CAPSENSE™ co-processor, and onboard AIROC™ Wi-Fi and Bluetooth® combo.
+
+Hardware
+********
+For more information about the PSOC™ Edge E84 MCUs and the PSOC™ Edge E84 Evaluation Kit:
+
+- `PSOC™ Edge Arm® Cortex® Multicore SoC Website`_
+- `PSOC™ Edge E84 Evaluation Kit Website`_
+
+Kit Features:
+=============
+
+- Cortex®-M55 CPU with Helium™ DSP
+- Advanced ML with Arm Ethos™-U55 NPU
+- Low-Power Cortex®-M33
+- NNLite ultra-low power NPU
+- Analog and Digital Microphones
+- State-of-the-Art Secured Enclave
+- Integrated Programmer/Debugger
+
+Kit Contents:
+=============
+
+- PSOC™ Edge E84 base board
+- PSOC™ Edge E84 SOM module
+- 4.3in capacitive touch display and USB camera module
+- USB Type C to Type-C cable
+- Two proximity sensor wires
+- Four stand-offs for Raspberry Pi compatible display
+- Quick start guide
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+Please refer to `kit_pse84_eval User Manual Website`_ for more details.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+The KIT-PSE84-EVAL includes an onboard programmer/debugger (`KitProg3`_) to provide debugging,
+flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and
+require a custom Infineon OpenOCD version, that supports KitProg3, to be installed.
+
+Please refer to the `ModusToolbox™ software installation guide`_ to install the
+Infineon OpenOCD and Edge Protect Security Suite (edgeprotecttools).
+
+Flashing
+========
+Applications for the ``kit_pse84_eval/pse846gps2dbzc4a/m33`` board target can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Applications for the ``kit_pse84_eval/pse846gps2dbzc4a/m55``
+board target need to be built using sysbuild to include the required application for the other core.
+
+Enter the following command to compile ``hello_world`` for the FLPR core:
+
+.. code-block:: console
+
+ west build -p -b kit_pse84_eval/pse846gps2dbzc4a/m55 --sysbuild
+
+Debugging
+=========
+The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool
+commands. There are multiple ways of doing this. The example below uses a permanent CMake argument
+to set the CMake variable ``OPENOCD``.
+
+ .. tabs::
+ .. group-tab:: Windows
+
+ .. code-block:: shell
+
+ # Run west config once to set permanent CMake argument
+ west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe
+
+ # Do a pristine build once after setting CMake argument
+ west build -b kit_pse84_eval/pse846gps2dbzc4a/m33 -p always samples/basic/blinky
+ west flash
+ west debug
+
+ .. group-tab:: Linux
+
+ .. code-block:: shell
+
+ # Run west config once to set permanent CMake argument
+ west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd
+
+ # Do a pristine build once after setting CMake argument
+ west build -b kit_pse84_eval/pse846gps2dbzc4a/m33 -p always samples/basic/blinky
+
+ west flash
+ west debug
+
+Once the gdb console starts after executing the west debug command, you may now set breakpoints and
+perform other standard GDB debugging on the PSOC E84 CM33 core.
+
+References
+**********
+
+- `PSOC™ Edge Arm® Cortex® Multicore SoC Website`_
+
+.. _PSOC™ Edge Arm® Cortex® Multicore SoC Website:
+ https://www.infineon.com/products/microcontroller/32-bit-psoc-arm-cortex/32-bit-psoc-edge-arm/psoc-edge-e84#Overview
+
+.. _PSOC™ Edge E84 Evaluation Kit Website:
+ https://www.infineon.com/evaluation-board/KIT-PSE84-EVAL
+
+.. _kit_pse84_eval User Manual Website:
+ https://www.infineon.com/assets/row/public/documents/30/44/infineon-kit-pse84-eval-qsg-usermanual-en.pdf
+
+.. _ModusToolbox™:
+ https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxsetup
+
+.. _ModusToolbox™ software installation guide:
+ https://www.Infineon.com/ModusToolboxInstallguide
+
+.. _KitProg3:
+ https://github.com/Infineon/KitProg3
diff --git a/boards/infineon/kit_pse84_eval/doc/kit_pse84_eval.webp b/boards/infineon/kit_pse84_eval/doc/kit_pse84_eval.webp
new file mode 100644
index 0000000..4262d40
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/doc/kit_pse84_eval.webp
Binary files differ
diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_common-pinctrl.dtsi b/boards/infineon/kit_pse84_eval/kit_pse84_eval_common-pinctrl.dtsi
new file mode 100644
index 0000000..c20aad6
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_common-pinctrl.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Configure pin control bias mode for uart2 pins */
+&p6_7_scb2_uart_tx{
+ drive-push-pull;
+};
+
+&p6_5_scb2_uart_rx {
+ input-enable;
+};
diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_common.dtsi b/boards/infineon/kit_pse84_eval/kit_pse84_eval_common.dtsi
new file mode 100644
index 0000000..e672305
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_common.dtsi
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include "kit_pse84_eval_common-pinctrl.dtsi"
+
+/ {
+ aliases {
+ sw0 = &user_bt;
+ watchdog0 = &watchdog0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_red: led_0 {
+ label = "LED_0";
+ gpios = <&gpio_prt16 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_green: led_1 {
+ label = "LED_1";
+ gpios = <&gpio_prt16 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_blue: led_2 {
+ label = "LED_2";
+ gpios = <&gpio_prt16 5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ user_bt: button_0 {
+ label = "SW_1";
+ gpios = <&gpio_prt8 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+ zephyr,code = <INPUT_KEY_0>;
+ };
+ };
+};
+
+uart2: &scb2 {
+ compatible = "infineon,cat1-uart-pdl";
+ status = "okay";
+ current-speed = <115200>;
+
+ clocks = <&peri0_group1_16bit_0>;
+
+ pinctrl-0 = <&p6_7_scb2_uart_tx &p6_5_scb2_uart_rx>;
+ pinctrl-names = "default";
+};
+
+&peri0_group1_16bit_0 {
+ status = "okay";
+ resource-type = <IFX_RSC_SCB>;
+ resource-instance = <2>;
+ clock-div = <1>;
+};
+
+&gpio_prt0 {
+ status = "okay";
+};
+
+&gpio_prt16 {
+ status = "okay";
+};
+
+&gpio_prt2 {
+ status = "okay";
+};
+
+&gpio_prt8 {
+ status = "okay";
+};
+
+&gpio_prt13 {
+ status = "okay";
+};
+
+&gpio_prt14 {
+ status = "okay";
+};
+
+&gpio_prt16 {
+ status = "okay";
+};
+
+&clk_iho {
+ status = "okay";
+ clock-frequency = <50000000>;
+};
+
+&path_mux0 {
+ status = "okay";
+};
+
+&path_mux1 {
+ status = "okay";
+};
+
+&path_mux2 {
+ status = "okay";
+};
+
+&path_mux3 {
+ status = "okay";
+};
+
+&path_mux4 {
+ status = "okay";
+};
+
+&path_mux5 {
+ status = "okay";
+};
+
+&clk_hf0 {
+ clocks = <&path_mux0>;
+ status = "okay";
+};
+
+&clk_hf1 {
+ clocks = <&path_mux2>;
+ status = "okay";
+};
+
+&clk_hf2 {
+ clocks = <&path_mux2>;
+ status = "okay";
+};
+
+&clk_hf3 {
+ clock-div = <IFX_CLK_HF_DIVIDE_BY_2>;
+ clocks = <&path_mux2>;
+ status = "okay";
+};
+
+&clk_hf4 {
+ clock-div = <IFX_CLK_HF_DIVIDE_BY_2>;
+ clocks = <&path_mux2>;
+ status = "okay";
+};
+
+&clk_hf5 {
+ clock-div = <IFX_CLK_HF_DIVIDE_BY_2>;
+ clocks = <&path_mux2>;
+ status = "okay";
+};
+
+&clk_hf6 {
+ clock-div = <IFX_CLK_HF_DIVIDE_BY_2>;
+ clocks = <&path_mux2>;
+ status = "okay";
+};
+
+&clk_hf7 {
+ clock-div = <IFX_CLK_HF_DIVIDE_BY_4>;
+ clocks = <&path_mux2>;
+ status = "okay";
+};
+
+&clk_hf8 {
+ clocks = <&path_mux3>;
+ status = "okay";
+};
+
+&clk_hf9 {
+ clock-div = <IFX_CLK_HF_DIVIDE_BY_5>;
+ clocks = <&path_mux2>;
+ status = "okay";
+};
+
+&clk_hf10 {
+ clock-div = <IFX_CLK_HF_DIVIDE_BY_4>;
+ clocks = <&path_mux2>;
+ status = "okay";
+};
+
+&clk_hf11 {
+ clocks = <&path_mux0>;
+ status = "okay";
+};
+
+&clk_hf12 {
+ clocks = <&path_mux1>;
+ status = "okay";
+};
+
+&clk_hf13 {
+ clock-div = <IFX_CLK_HF_DIVIDE_BY_4>;
+ clocks = <&path_mux2>;
+ status = "okay";
+};
+
+&dpll_hp {
+ status = "okay";
+};
diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.dts b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.dts
new file mode 100644
index 0000000..c3f66a4
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <infineon/edge/mpns/pse846gps2dbzc4a_s.dtsi>
+#include <infineon/edge/pse84/pse84.cm33.dtsi>
+#include <infineon/edge/pse84/system_clocks.dtsi>
+
+#include "kit_pse84_eval_common.dtsi"
+#include "kit_pse84_eval_memory_map.dtsi"
+
+/ {
+ model = "kit_pse84_eval";
+ compatible = "kit_pse84_eval";
+
+ aliases {
+ led0 = &led_red;
+ led1 = &led_green;
+ led2 = &led_blue;
+ };
+
+ chosen {
+ zephyr,flash = &m33s_xip;
+ zephyr,sram = &m33s_data;
+ zephyr,console = &uart2;
+ zephyr,shell-uart = &uart2;
+ };
+};
diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.yaml b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.yaml
new file mode 100644
index 0000000..4ed08e4
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: kit_pse84_eval/pse846gps2dbzc4a/m33
+name: PSOC Edge84 Evaluation Kit (M33_S)
+type: mcu
+arch: arm
+sysbuild: true
+toolchain:
+ - zephyr
+supported:
+ - clock_control
+ - gpio
+ - pin_ctrl
+ - uart
diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33_defconfig b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33_defconfig
new file mode 100644
index 0000000..cf7084e
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33_defconfig
@@ -0,0 +1,37 @@
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable FPU
+CONFIG_FPU=y
+CONFIG_FPU_SHARING=y
+
+# General configuration
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_BUILD_OUTPUT_HEX=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable GPIO driver
+CONFIG_GPIO=y
+
+# Enable Clock Control driver
+CONFIG_CLOCK_CONTROL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable assert
+CONFIG_ASSERT=y
+
+CONFIG_ARM_TRUSTZONE_M=y
+CONFIG_ARM_MPU=y
+
+# Build a Secure firmware image
+CONFIG_TRUSTED_EXECUTION_SECURE=y
diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.dts b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.dts
new file mode 100644
index 0000000..506c0a8
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.dts
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <infineon/edge/mpns/pse846gps2dbzc4a.dtsi>
+#include <infineon/edge/pse84/pse84.cm55.dtsi>
+#include <infineon/edge/pse84/system_clocks.dtsi>
+
+#include "kit_pse84_eval_common.dtsi"
+#include "kit_pse84_eval_memory_map.dtsi"
+
+/ {
+ model = "kit_pse84_eval";
+ compatible = "kit_pse84_eval";
+
+ aliases {
+ led0 = &led_red;
+ led1 = &led_green;
+ led2 = &led_blue;
+ };
+
+ chosen {
+ /* m55_xip is used in the pse84_boot.c file for m55 core startup
+ * If a different region is assigned here, it also needs to be updated at:
+ * soc/infineon/edge/pse84/security_config/pse84_boot.c
+ */
+ zephyr,flash = &m55_xip;
+ zephyr,sram = &m55_data;
+ zephyr,console = &uart2;
+ zephyr,shell-uart = &uart2;
+ };
+};
diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.yaml b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.yaml
new file mode 100644
index 0000000..af184f3
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: kit_pse84_eval/pse846gps2dbzc4a/m55
+name: PSOC Edge84 Evaluation Kit (M55)
+type: mcu
+arch: arm
+sysbuild: true
+toolchain:
+ - zephyr
+supported:
+ - clock_control
+ - gpio
+ - pin_ctrl
+ - uart
diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55_defconfig b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55_defconfig
new file mode 100644
index 0000000..b8b9410
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55_defconfig
@@ -0,0 +1,32 @@
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable FPU
+CONFIG_FPU=y
+CONFIG_FPU_SHARING=y
+
+# General configuration
+CONFIG_BUILD_OUTPUT_HEX=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable GPIO driver
+CONFIG_GPIO=y
+
+# Enable Clock Control driver
+CONFIG_CLOCK_CONTROL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable assert
+CONFIG_ASSERT=y
+
+CONFIG_CODE_DATA_RELOCATION=y
diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_memory_map.dtsi b/boards/infineon/kit_pse84_eval/kit_pse84_eval_memory_map.dtsi
new file mode 100644
index 0000000..ab3a8b8
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_memory_map.dtsi
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ /* Default SRAM(1MB) assignment
+ * - Lowest 4kb reserved for the Extended boot
+ * - 4kb shared between CM33 secure project and secure enclave
+ * - 212 kB allocated to CM33 Secure code
+ * - 132 kB allocated to CM33 Secure data
+ * - 404 kB allocated to CM33 Non-Secure code
+ * - 256 kB allocated to the CM33 Non-Secure data
+ * - 4 kB allocated to shared memory for each core (cm33_s, cm33 and cm55)
+ */
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ extended_boot_sram_reserved: memory@34000000 {
+ reg = <0x34000000 DT_SIZE_K(4)>;
+ };
+
+ m33s_shared: memory@34001000 {
+ reg = <0x34001000 DT_SIZE_K(4)>;
+ };
+
+ m33s_code: memory@34002000 {
+ reg = <0x34002000 DT_SIZE_K(212)>;
+ };
+
+ m33s_data: memory@34037000 {
+ reg = <0x34037000 DT_SIZE_K(132)>;
+ };
+
+ m33_code: memory@24058000 {
+ reg = <0x24058000 DT_SIZE_K(404)>;
+ };
+
+ m33_data: memory@240bd000 {
+ reg = <0x240bd000 DT_SIZE_K(256)>;
+ };
+
+ m33s_allocatable_shared: memory@340fd000 {
+ compatible = "zephyr,memory-region", "mmio-sram";
+ zephyr,memory-region = "SHARED_MEMORY_SEC";
+ reg = <0x340fd000 DT_SIZE_K(4)>;
+ };
+
+ m33_allocatable_shared: memory@240fe000 {
+ compatible = "zephyr,memory-region", "mmio-sram";
+ zephyr,memory-region = "SHARED_MEMORY";
+ reg = <0x240fe000 DT_SIZE_K(4)>;
+ };
+
+ m55_allocatable_shared: memory@240ff000 {
+ reg = <0x240ff000 DT_SIZE_K(4)>;
+ };
+
+ m55_data: memory@26100000 {
+ reg = <0x26100000 DT_SIZE_K(256)>;
+ };
+ };
+
+ /* Default Flash memory(16MB) assignment
+ * - Lowest 1mb reserved for Storage
+ * - 2mb for each of the cores(cm33_s, cm33 and cm55)
+
+ */
+ flash_controller: flash_controller@40250000 {
+ compatible = "infineon,cat1-qspi-flash-mtb-hal";
+ reg = <0x40250000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash0: flash0@8000000 {
+ compatible = "soc-nv-flash";
+ reg = <0x08000000 DT_SIZE_M(16)>;
+ write-block-size = <256>;
+ erase-block-size = <65536>;
+
+ partitions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fixed-partitions";
+
+ storage: storage@0 {
+ label = "storage";
+ reg = <0 DT_SIZE_M(1)>;
+ };
+
+ m33s_header: m33s_header@60100000 {
+ reg = <0x60100000 0x400>;
+ };
+
+ m33s_xip: m33s_xip@70100400 {
+ reg = <0x70100400 DT_SIZE_M(2)>;
+ };
+
+ m33_xip: m33_xip@8300000 {
+ reg = <0x8300000 DT_SIZE_M(2)>;
+ };
+
+ m55_xip: m33_xip@60500000 {
+ reg = <0x60500000 DT_SIZE_M(2)>;
+ };
+ };
+ };
+ };
+};
diff --git a/boards/infineon/kit_pse84_eval/support/openocd.cfg b/boards/infineon/kit_pse84_eval/support/openocd.cfg
new file mode 100644
index 0000000..ada2b2e
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/support/openocd.cfg
@@ -0,0 +1,42 @@
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+set ENABLE_CM55 1
+set ENABLE_CM33 1
+
+source [find interface/kitprog3.cfg]
+transport select swd
+
+if { [info exists _ZEPHYR_BOARD_SERIAL] } {
+ adapter serial $_ZEPHYR_BOARD_SERIAL
+}
+
+if { [info exists WEST_ATTACH] } {
+ set ENABLE_ACQUIRE 0
+}
+
+source [find target/infineon/pse84xgxs2.cfg]
+cat1d.cm55 configure -rtos auto -rtos-wipe-on-reset-halt 1
+cat1d.cm33 configure -rtos auto -rtos-wipe-on-reset-halt 1
+gdb_breakpoint_override hard
+
+if { [info exists WEST_ATTACH] } {
+ set _RESET 0
+} else {
+ set _RESET 1
+}
+
+if {$_RESET} {
+ cat1d.cm55 configure -event gdb-attach {
+ reset_halt cm55
+ }
+
+ cat1d.cm33 configure -event gdb-attach {
+ cat1d.cm33 cortex_m vector_catch reset
+ reset run
+ cat1d.cm33 arp_waitstate halted 8000
+ cat1d.cm33 cortex_m vector_catch none
+ }
+}
diff --git a/boards/infineon/kit_pse84_eval/support/qspi_config.cfg b/boards/infineon/kit_pse84_eval/support/qspi_config.cfg
new file mode 100644
index 0000000..4b5f461
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/support/qspi_config.cfg
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+set SMIF_BANKS {
+ 1 {addr 0x60000000 size 0x1000000 psize 0x0000100 esize 0x0010000}
+}
diff --git a/boards/infineon/kit_pse84_eval/sysbuild.cmake b/boards/infineon/kit_pse84_eval/sysbuild.cmake
new file mode 100644
index 0000000..01bde13
--- /dev/null
+++ b/boards/infineon/kit_pse84_eval/sysbuild.cmake
@@ -0,0 +1,14 @@
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if(SB_CONFIG_BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M55)
+ ExternalZephyrProject_Add(
+ APPLICATION enable_cm55
+ SOURCE_DIR ${ZEPHYR_BASE}/samples/basic/minimal
+ BOARD kit_pse84_eval/pse846gps2dbzc4a/m33
+ )
+
+ set_config_bool(enable_cm55 CONFIG_SOC_PSE84_M55_ENABLE 1)
+endif()
