doc: release: migration guide: 3.6: add note on stm32h7 CAN domain clk
Add a note describing the new default for the STM32H7 FDCAN CAN controller
domain/kernel clock and how to override it.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
diff --git a/doc/releases/migration-guide-3.6.rst b/doc/releases/migration-guide-3.6.rst
index 22321e8..1156cc9 100644
--- a/doc/releases/migration-guide-3.6.rst
+++ b/doc/releases/migration-guide-3.6.rst
@@ -159,6 +159,18 @@
* :dtcompatible:`ti,lmp90099`
* :dtcompatible:`ti,lmp90100`
+* The :dtcompatible:`st,stm32h7-fdcan` CAN controller driver now supports configuring the
+ domain/kernel clock via devicetree. Previously, the driver only supported using the PLL1_Q clock
+ for kernel clock, but now it defaults to the HSE clock, which is the chip default. Boards that
+ use the PLL1_Q clock for FDCAN will need to override the ``clocks`` property as follows:
+
+ .. code-block:: devicetree
+
+ &fdcan1 {
+ clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
+ <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
+ };
+
Power Management
================
