dts: arm: st: stm32f7: remove U suffix from "resets" in DTSI
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi
index 6b7c7ce..8e1947e 100644
--- a/dts/arm/st/f7/stm32f7.dtsi
+++ b/dts/arm/st/f7/stm32f7.dtsi
@@ -263,7 +263,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 4)>;
- resets = <&rctl STM32_RESET(APB2, 4U)>;
+ resets = <&rctl STM32_RESET(APB2, 4)>;
interrupts = <37 0>;
status = "disabled";
};
@@ -272,7 +272,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
- resets = <&rctl STM32_RESET(APB1, 17U)>;
+ resets = <&rctl STM32_RESET(APB1, 17)>;
interrupts = <38 0>;
status = "disabled";
};
@@ -281,7 +281,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1, 18U)>;
+ resets = <&rctl STM32_RESET(APB1, 18)>;
interrupts = <39 0>;
status = "disabled";
};
@@ -290,7 +290,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1, 19U)>;
+ resets = <&rctl STM32_RESET(APB1, 19)>;
interrupts = <52 0>;
status = "disabled";
};
@@ -299,7 +299,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
- resets = <&rctl STM32_RESET(APB1, 20U)>;
+ resets = <&rctl STM32_RESET(APB1, 20)>;
interrupts = <53 0>;
status = "disabled";
};
@@ -308,7 +308,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 5)>;
- resets = <&rctl STM32_RESET(APB2, 5U)>;
+ resets = <&rctl STM32_RESET(APB2, 5)>;
interrupts = <71 0>;
status = "disabled";
};
@@ -317,7 +317,7 @@
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 30)>;
- resets = <&rctl STM32_RESET(APB1, 30U)>;
+ resets = <&rctl STM32_RESET(APB1, 30)>;
interrupts = <82 0>;
status = "disabled";
};
@@ -326,7 +326,7 @@
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 31)>;
- resets = <&rctl STM32_RESET(APB1, 31U)>;
+ resets = <&rctl STM32_RESET(APB1, 31)>;
interrupts = <83 0>;
status = "disabled";
};
@@ -431,7 +431,7 @@
reg = <0x40010000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 0)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 0U)>;
+ resets = <&rctl STM32_RESET(APB2, 0)>;
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
@@ -455,7 +455,7 @@
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 0)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 0U)>;
+ resets = <&rctl STM32_RESET(APB1, 0)>;
interrupts = <28 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -484,7 +484,7 @@
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 1U)>;
+ resets = <&rctl STM32_RESET(APB1, 1)>;
interrupts = <29 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -513,7 +513,7 @@
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 2)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 2U)>;
+ resets = <&rctl STM32_RESET(APB1, 2)>;
interrupts = <30 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -542,7 +542,7 @@
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 3)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 3U)>;
+ resets = <&rctl STM32_RESET(APB1, 3)>;
interrupts = <50 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -571,7 +571,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 4U)>;
+ resets = <&rctl STM32_RESET(APB1, 4)>;
interrupts = <54 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -588,7 +588,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 5U)>;
+ resets = <&rctl STM32_RESET(APB1, 5)>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -605,7 +605,7 @@
reg = <0x40010400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 1)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 1U)>;
+ resets = <&rctl STM32_RESET(APB2, 1)>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
@@ -629,7 +629,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 16U)>;
+ resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <24 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -652,7 +652,7 @@
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 17)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 17U)>;
+ resets = <&rctl STM32_RESET(APB2, 17)>;
interrupts = <25 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -675,7 +675,7 @@
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 18)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 18U)>;
+ resets = <&rctl STM32_RESET(APB2, 18)>;
interrupts = <26 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -698,7 +698,7 @@
reg = <0x40001800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 6)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 6U)>;
+ resets = <&rctl STM32_RESET(APB1, 6)>;
interrupts = <43 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -721,7 +721,7 @@
reg = <0x40001c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 7)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 7U)>;
+ resets = <&rctl STM32_RESET(APB1, 7)>;
interrupts = <44 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -744,7 +744,7 @@
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 8)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 8U)>;
+ resets = <&rctl STM32_RESET(APB1, 8)>;
interrupts = <45 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -902,7 +902,7 @@
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 11)>,
<&rcc STM32_SRC_PLL_Q SDMMC1_SEL(0)>;
- resets = <&rctl STM32_RESET(APB2, 11U)>;
+ resets = <&rctl STM32_RESET(APB2, 11)>;
interrupts = <49 0>;
status = "disabled";
};
diff --git a/dts/arm/st/f7/stm32f722.dtsi b/dts/arm/st/f7/stm32f722.dtsi
index 8dd1b0f..b8e619a 100644
--- a/dts/arm/st/f7/stm32f722.dtsi
+++ b/dts/arm/st/f7/stm32f722.dtsi
@@ -37,7 +37,7 @@
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 7)>,
<&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
- resets = <&rctl STM32_RESET(APB2, 7U)>;
+ resets = <&rctl STM32_RESET(APB2, 7)>;
interrupts = <103 0>;
status = "disabled";
};
diff --git a/dts/arm/st/f7/stm32f746.dtsi b/dts/arm/st/f7/stm32f746.dtsi
index 7a5d819..992fd56 100644
--- a/dts/arm/st/f7/stm32f746.dtsi
+++ b/dts/arm/st/f7/stm32f746.dtsi
@@ -17,7 +17,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_err";
clocks = <&rcc STM32_CLOCK(APB2, 26)>;
- resets = <&rctl STM32_RESET(APB2, 26U)>;
+ resets = <&rctl STM32_RESET(APB2, 26)>;
status = "disabled";
};
};
diff --git a/dts/arm/st/f7/stm32f765.dtsi b/dts/arm/st/f7/stm32f765.dtsi
index ca9312f..e356f72 100644
--- a/dts/arm/st/f7/stm32f765.dtsi
+++ b/dts/arm/st/f7/stm32f765.dtsi
@@ -98,7 +98,7 @@
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 7)>,
<&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
- resets = <&rctl STM32_RESET(APB2, 7U)>;
+ resets = <&rctl STM32_RESET(APB2, 7)>;
interrupts = <103 0>;
status = "disabled";
};
diff --git a/dts/arm/st/f7/stm32f767.dtsi b/dts/arm/st/f7/stm32f767.dtsi
index bccc20d..0223783 100644
--- a/dts/arm/st/f7/stm32f767.dtsi
+++ b/dts/arm/st/f7/stm32f767.dtsi
@@ -18,7 +18,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_err";
clocks = <&rcc STM32_CLOCK(APB2, 26)>;
- resets = <&rctl STM32_RESET(APB2, 26U)>;
+ resets = <&rctl STM32_RESET(APB2, 26)>;
status = "disabled";
};
