| commit | 24148718fc6e8f36d7465d374a3b8f06e8543c22 | [log] [tgz] |
|---|---|---|
| author | Daniel Leung <daniel.leung@intel.com> | Mon Aug 21 12:45:20 2023 -0700 |
| committer | Anas Nashif <anas.nashif@intel.com> | Sat Aug 26 16:50:40 2023 -0400 |
| tree | 42a36da5a4d0b85c5bad3bbc2cceaea53e9ef016 | |
| parent | b6ccbae58dc4b2a85b0936272765fbdd84ca90ba [diff] |
xtensa: mmu: cache common data and heap if !XTENSA_RPO_CACHE If CONFIG_XTENSA_RPO_CACHE is not enabled, it can be assumed that memory is not double mapped in hardware for cached and uncached access. So we can specify those regions to have cache via TLB. Signed-off-by: Daniel Leung <daniel.leung@intel.com>