api/spi: Add EEPROM configuration bit
EEPROM read mode is a specific mode where the controller will TX a
command to the slave, and once done, will read as many bytes requested.
The gain relies in the controller generating all necessary dummy bytes
by itself to read data the from slave, it will only generate RX
interrupts. Thus reducing CPU work.
Obviously TX and RX buffers should be relevantly provided by the user.
If not supported by the controller, the driver can still work (it will
have to generate the dummy bytes) and thus -EINVAL should not be
returned for that configuration bit.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
diff --git a/include/spi.h b/include/spi.h
index be10771..6a7058f 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -114,6 +114,11 @@
* properly called.
*/
#define SPI_LOCK_ON BIT(14)
+/* Select EEPROM read mode on master controller.
+ * If not supported by the controller, the driver will have to emulate
+ * the mode and thus should never return -EINVAL on that configuration)
+ */
+#define SPI_EEPROM_MODE BIT(15)
/**
* @brief SPI Chip Select control structure
@@ -146,15 +151,15 @@
* lines [ 11 : 12 ] - MISO lines: Single/Dual/Quad.
* cs_hold [ 13 ] - Hold on the CS line if possible.
* lock_on [ 14 ] - Keep ressource locked for the caller.
- * RESERVED [ 15 ] - Unused yet
+ * eeprom [ 15 ] - EEPROM mode.
*
* slave is the slave number from 0 to host constoller slave limit.
*
* cs is a valid pointer on a struct spi_cs_control is CS line is
* emulated through a gpio line, or NULL otherwise.
*
- * Note: cs_hold and lock_on can be changed between consecutive transceive
- * call.
+ * Note: cs_hold, lock_on and eeprom_rx can be changed between consecutive
+ * transceive call.
*/
struct spi_config {
struct device *dev;
