drivers: clock_control: add clock_control support for kit_pse84_eval
- add support for kit_pse84_eval board
- refactor infineon,fixed-clock binding
- refactor infineon,fixed-factor binding
- refactor infinein,peri-div binding
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts
index 29f4694..755b120 100644
--- a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts
+++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts
@@ -39,8 +39,9 @@
&peri0_group4_8bit_0 {
status = "okay";
- scb-block = <3>;
- div-value = <109>;
+ resource-type = <IFX_RSC_SCB>;
+ resource-instance = <3>;
+ clock-div = <109>;
};
&path_mux0 {
diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts
index 49dd081..6a12db4 100644
--- a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts
+++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts
@@ -39,8 +39,9 @@
&peri0_group4_8bit_0 {
status = "okay";
- scb-block = <3>;
- div-value = <109>;
+ resource-type = <IFX_RSC_SCB>;
+ resource-instance = <3>;
+ clock-div = <109>;
};
&path_mux0 {
diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt
index 659c058..c5e9c9e 100644
--- a/drivers/clock_control/CMakeLists.txt
+++ b/drivers/clock_control/CMakeLists.txt
@@ -27,9 +27,9 @@
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clock_calibration.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32m1_pcc.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT1 clock_control_ifx_cat1.c)
-zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_FIXED_CLOCK clock_control_ifx_cat1_fixed_clock.c)
-zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_FIXED_FACTOR_CLOCK clock_control_ifx_cat1_fixed_factor_clock.c)
-zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_PERI_CLOCK clock_control_ifx_cat1_peri_clock.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_FIXED_CLOCK clock_control_ifx_fixed_clock.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_FIXED_FACTOR_CLOCK clock_control_ifx_fixed_factor_clock.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_PERI_CLOCK clock_control_ifx_peri_clock.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAM clock_control_sam_pmc.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAMA7G5 clock_control_sama7g5_pmc.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAMA7G5 clock_control_sama7g5_sckc.c)
diff --git a/drivers/clock_control/Kconfig.ifx_cat1 b/drivers/clock_control/Kconfig.ifx_cat1
index 522c3cd..36aee16 100644
--- a/drivers/clock_control/Kconfig.ifx_cat1
+++ b/drivers/clock_control/Kconfig.ifx_cat1
@@ -12,26 +12,23 @@
help
This option enables the clock control driver for Infineon CAT1 family.
-config CLOCK_CONTROL_IFX_CAT1_FIXED_CLOCK
+config CLOCK_CONTROL_IFX_FIXED_CLOCK
bool "Infineon CAT1 Fixed clock driver"
default y
- depends on SOC_FAMILY_INFINEON_CAT1
depends on DT_HAS_INFINEON_FIXED_CLOCK_ENABLED
help
This option enables the Fixed clock driver for Infineon CAT1 family.
-config CLOCK_CONTROL_IFX_CAT1_FIXED_FACTOR_CLOCK
+config CLOCK_CONTROL_IFX_FIXED_FACTOR_CLOCK
bool "Infineon CAT1 Fixed factor clock driver"
default y
- depends on SOC_FAMILY_INFINEON_CAT1
depends on DT_HAS_INFINEON_FIXED_FACTOR_CLOCK_ENABLED
help
This option enables the Fixed clock driver for Infineon CAT1 family.
-config CLOCK_CONTROL_IFX_CAT1_PERI_CLOCK
+config CLOCK_CONTROL_IFX_PERI_CLOCK
bool "Infineon CAT1 Fixed clock driver"
default y
- depends on SOC_FAMILY_INFINEON_CAT1
- depends on DT_HAS_INFINEON_CAT1_PERI_DIV_ENABLED
+ depends on DT_HAS_INFINEON_PERI_DIV_ENABLED
help
This option enables the Peripheral clock driver for Infineon CAT1 family.
diff --git a/drivers/clock_control/clock_control_ifx_fixed_clock.c b/drivers/clock_control/clock_control_ifx_fixed_clock.c
index 06fa65f..6f97a4c 100644
--- a/drivers/clock_control/clock_control_ifx_fixed_clock.c
+++ b/drivers/clock_control/clock_control_ifx_fixed_clock.c
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
- * an affiliate of Cypress Semiconductor Corporation
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,33 +13,98 @@
#include <zephyr/kernel.h>
#include <stdlib.h>
+#include <infineon_kconfig.h>
#include <zephyr/drivers/clock_control/clock_control_ifx_cat1.h>
-#include <zephyr/dt-bindings/clock/ifx_clock_source_def.h>
+#include <zephyr/dt-bindings/clock/ifx_clock_source_common.h>
+#include <zephyr/dt-bindings/clock/ifx_clock_source_boards.h>
+
#include <cy_sysclk.h>
#define DT_DRV_COMPAT infineon_fixed_clock
struct fixed_rate_clock_config {
uint32_t rate;
- uint32_t id; /* ifx_cat1_clock_block */
+ uint32_t system_clock; /* ifx_cat1_clock_block */
};
+__WEAK void ifx_clock_startup_error(uint32_t error)
+{
+ (void)error; /* Suppress the compiler warning */
+ while (1) {
+ }
+}
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp))
+void ifx_clk_dpll_hp0_init(void)
+{
+#define CY_CFG_SYSCLK_PLL_ERROR 3
+
+ static cy_stc_dpll_hp_config_t dpll_hp_config = {
+ .pDiv = 0,
+ .nDiv = 15,
+ .kDiv = 1,
+ .nDivFract = 0,
+ .freqModeSel = CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL,
+ .ivrTrim = 0x8U,
+ .clkrSel = 0x1U,
+ .alphaCoarse = 0xCU,
+ .betaCoarse = 0x5U,
+ .flockThresh = 0x3U,
+ .flockWait = 0x6U,
+ .flockLkThres = 0x7U,
+ .flockLkWait = 0x4U,
+ .alphaExt = 0x14U,
+ .betaExt = 0x14U,
+ .lfEn = 0x1U,
+ .dcEn = 0x1U,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+ };
+ static cy_stc_pll_manual_config_t dpll_config = {
+ .hpPllCfg = &dpll_hp_config,
+ };
+
+#if !defined(CY_PDL_TZ_ENABLED)
+ if (Cy_SysClk_PllIsEnabled(SRSS_DPLL_HP_0_PATH_NUM)) {
+ return;
+ }
+#endif
+ Cy_SysClk_PllDisable(SRSS_DPLL_HP_0_PATH_NUM);
+ if (CY_SYSCLK_SUCCESS !=
+ Cy_SysClk_PllManualConfigure(SRSS_DPLL_HP_0_PATH_NUM, &dpll_config)) {
+ ifx_clock_startup_error(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_DPLL_HP_0_PATH_NUM, 10000u)) {
+ ifx_clock_startup_error(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+}
+#endif
+
static int fixed_rate_clk_init(const struct device *dev)
{
const struct fixed_rate_clock_config *const config = dev->config;
- switch (config->id) {
+ switch (config->system_clock) {
- case IFX_CAT1_CLOCK_BLOCK_IMO:
+ case IFX_IMO:
break;
- case IFX_CAT1_CLOCK_BLOCK_FLL:
+ case IFX_FLL:
break;
- case IFX_CAT1_CLOCK_BLOCK_IHO:
+ case IFX_IHO:
Cy_SysClk_IhoEnable();
break;
+ case IFX_PILO:
+ Cy_SysClk_PiloEnable();
+ break;
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp))
+ case IFX_DPLL500:
+ ifx_clk_dpll_hp0_init();
+ SystemCoreClockUpdate();
+ break;
+#endif
default:
break;
}
@@ -47,13 +112,12 @@
return 0;
}
-#define FIXED_CLK_INIT(idx) \
- static const struct fixed_rate_clock_config fixed_rate_clock_config_##idx = { \
- .rate = DT_INST_PROP(idx, clock_frequency), \
- .id = DT_INST_PROP(idx, clock_block), \
+#define FIXED_CLK_INIT(n) \
+ static const struct fixed_rate_clock_config fixed_rate_clock_config_##n = { \
+ .rate = DT_INST_PROP(n, clock_frequency), \
+ .system_clock = DT_INST_PROP(n, system_clock), \
}; \
- DEVICE_DT_INST_DEFINE(idx, fixed_rate_clk_init, NULL, NULL, \
- &fixed_rate_clock_config_##idx, PRE_KERNEL_1, \
- CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL);
+ DEVICE_DT_INST_DEFINE(n, fixed_rate_clk_init, NULL, NULL, &fixed_rate_clock_config_##n, \
+ PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(FIXED_CLK_INIT)
diff --git a/drivers/clock_control/clock_control_ifx_fixed_factor_clock.c b/drivers/clock_control/clock_control_ifx_fixed_factor_clock.c
index afc1fec..a939a7c 100644
--- a/drivers/clock_control/clock_control_ifx_fixed_factor_clock.c
+++ b/drivers/clock_control/clock_control_ifx_fixed_factor_clock.c
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
- * an affiliate of Cypress Semiconductor Corporation
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,8 +13,11 @@
#include <zephyr/kernel.h>
#include <stdlib.h>
+#include <infineon_kconfig.h>
#include <zephyr/drivers/clock_control/clock_control_ifx_cat1.h>
-#include <zephyr/dt-bindings/clock/ifx_clock_source_def.h>
+#include <zephyr/dt-bindings/clock/ifx_clock_source_common.h>
+#include <zephyr/dt-bindings/clock/ifx_clock_source_boards.h>
+
#include <cy_sysclk.h>
#define DT_DRV_COMPAT infineon_fixed_factor_clock
@@ -24,21 +27,33 @@
uint32_t block; /* ifx_cat1_clock_block */
uint32_t instance;
uint32_t source_path;
- uint32_t source_instance;
+ uint32_t source_block;
};
static int fixed_factor_clk_init(const struct device *dev)
{
const struct fixed_factor_clock_config *const config = dev->config;
+ uint32_t source_instance;
+
+ switch (config->source_block) {
+
+ case IFX_DPLL250_1:
+ source_instance = 1;
+ break;
+
+ default:
+ source_instance = 0;
+ break;
+ }
switch (config->block) {
- case IFX_CAT1_CLOCK_BLOCK_PATHMUX:
+ case IFX_PATHMUX:
Cy_SysClk_ClkPathSetSource(config->instance, config->source_path);
break;
- case IFX_CAT1_CLOCK_BLOCK_HF:
- Cy_SysClk_ClkHfSetSource(config->instance, config->source_instance);
+ case IFX_HF:
+ Cy_SysClk_ClkHfSetSource(config->instance, source_instance);
Cy_SysClk_ClkHfSetDivider(config->instance, config->divider);
Cy_SysClk_ClkHfEnable(config->instance);
break;
@@ -50,16 +65,16 @@
return 0;
}
-#define FIXED_CLK_INIT(idx) \
- static const struct fixed_factor_clock_config fixed_factor_clock_config_##idx = { \
- .divider = DT_INST_PROP_OR(idx, clock_divider, 1u), \
- .block = DT_INST_PROP(idx, clock_block), \
- .instance = DT_INST_PROP(idx, clock_instance), \
- .source_path = DT_INST_PROP_OR(idx, source_path, 1u), \
- .source_instance = DT_INST_PROP_BY_PHANDLE(idx, clocks, clock_instance), \
+#define FIXED_CLK_INIT(n) \
+ static const struct fixed_factor_clock_config fixed_factor_clock_config_##n = { \
+ .divider = DT_INST_PROP_OR(n, clock_div, 1u), \
+ .block = DT_INST_PROP(n, system_clock), \
+ .instance = DT_INST_PROP(n, instance), \
+ .source_path = DT_INST_PROP_OR(n, source_path, 1u), \
+ .source_block = DT_INST_PROP_BY_PHANDLE(n, clocks, system_clock), \
}; \
- DEVICE_DT_INST_DEFINE(idx, fixed_factor_clk_init, NULL, NULL, \
- &fixed_factor_clock_config_##idx, PRE_KERNEL_1, \
+ DEVICE_DT_INST_DEFINE(n, fixed_factor_clk_init, NULL, NULL, \
+ &fixed_factor_clock_config_##n, PRE_KERNEL_1, \
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(FIXED_CLK_INIT)
diff --git a/drivers/clock_control/clock_control_ifx_peri_clock.c b/drivers/clock_control/clock_control_ifx_peri_clock.c
index 4b7b904..bbd1b43 100644
--- a/drivers/clock_control/clock_control_ifx_peri_clock.c
+++ b/drivers/clock_control/clock_control_ifx_peri_clock.c
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
- * an affiliate of Cypress Semiconductor Corporation
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,12 +9,16 @@
* @brief Peripheral Clock control driver for Infineon CAT1 MCU family.
*/
-#define DT_DRV_COMPAT infineon_cat1_peri_div
+#define DT_DRV_COMPAT infineon_peri_div
-#include <zephyr/drivers/clock_control/clock_control_ifx_cat1.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/kernel.h>
#include <stdlib.h>
+
+#include <infineon_kconfig.h>
+#include <zephyr/drivers/clock_control/clock_control_ifx_cat1.h>
+#include <zephyr/dt-bindings/clock/ifx_clock_source_common.h>
+
#include <cy_sysclk.h>
#include <cy_systick.h>
@@ -52,6 +56,14 @@
} else {
clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB0_PCLK_CLOCK + block_num - 1);
}
+#elif defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
+ if (block_num == 0) {
+ clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB0_PCLK_CLOCK);
+ } else if (block_num == 1) {
+ clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB1_PCLK_CLOCK);
+ } else {
+ clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB0_PCLK_CLOCK + block_num - 1);
+ }
#else
clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB0_PCLK_CLOCK + block_num);
#endif
@@ -62,27 +74,41 @@
{
struct ifx_cat1_peri_clock_data *const data = dev->data;
- en_clk_dst_t clk_idx = ifx_cat1_scb_get_clock_index(data->hw_resource.block_num);
+ if (data->hw_resource.type == IFX_RSC_SCB) {
+ en_clk_dst_t clk_idx = ifx_cat1_scb_get_clock_index(data->hw_resource.block_num);
- ifx_cat1_utils_peri_pclk_set_divider(clk_idx, &data->clock, data->divider - 1);
- ifx_cat1_utils_peri_pclk_assign_divider(clk_idx, &data->clock);
- ifx_cat1_utils_peri_pclk_enable_divider(clk_idx, &data->clock);
+ ifx_cat1_utils_peri_pclk_set_divider(clk_idx, &data->clock, data->divider - 1);
+ ifx_cat1_utils_peri_pclk_assign_divider(clk_idx, &data->clock);
+ ifx_cat1_utils_peri_pclk_enable_divider(clk_idx, &data->clock);
+ } else {
+ return -EINVAL;
+ }
return 0;
}
+#if defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
+#define PERI_CLOCK_INIT(n) \
+ .clock = { \
+ .block = IFX_CAT1_PERIPHERAL_GROUP_ADJUST(DT_INST_PROP_BY_IDX(n, peri_group, 0), \
+ DT_INST_PROP_BY_IDX(n, peri_group, 1), \
+ DT_INST_PROP(n, div_type)), \
+ .channel = DT_INST_PROP(n, channel), \
+ },
+#else
+#define PERI_CLOCK_INIT(n) \
+ .clock = { \
+ .block = IFX_CAT1_PERIPHERAL_GROUP_ADJUST(DT_INST_PROP_BY_IDX(n, peri_group, 1), \
+ DT_INST_PROP(n, div_type)), \
+ .channel = DT_INST_PROP(n, channel), \
+ },
+#endif
+
#define INFINEON_CAT1_PERI_CLOCK_INIT(n) \
static struct ifx_cat1_peri_clock_data ifx_cat1_peri_clock##n##_data = { \
- .clock = \
- { \
- .block = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
- DT_INST_PROP_BY_IDX(n, clk_dst, 1), \
- DT_INST_PROP(n, div_type)), \
- .channel = DT_INST_PROP(n, div_num), \
- }, \
- .divider = DT_INST_PROP(n, div_value), \
- .hw_resource = {.type = IFX_CAT1_RSC_SCB, \
- .block_num = DT_INST_PROP(n, scb_block)}, \
+ PERI_CLOCK_INIT(n).divider = DT_INST_PROP(n, clock_div), \
+ .hw_resource = {.type = DT_INST_PROP(n, resource_type), \
+ .block_num = DT_INST_PROP(n, resource_instance)}, \
}; \
\
DEVICE_DT_INST_DEFINE(n, &ifx_cat1_peri_clock_init, NULL, &ifx_cat1_peri_clock##n##_data, \
diff --git a/drivers/serial/uart_ifx_cat1_pdl.c b/drivers/serial/uart_ifx_cat1_pdl.c
index 369e3c5..738b081 100644
--- a/drivers/serial/uart_ifx_cat1_pdl.c
+++ b/drivers/serial/uart_ifx_cat1_pdl.c
@@ -24,6 +24,7 @@
#include <cy_sysint.h>
#include <zephyr/drivers/clock_control/clock_control_ifx_cat1.h>
+#include <zephyr/dt-bindings/clock/ifx_clock_source_common.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(uart_ifx_cat1, CONFIG_UART_LOG_LEVEL);
@@ -731,7 +732,7 @@
int ret;
/* Dedicate SCB HW resource */
- data->hw_resource.type = IFX_CAT1_RSC_SCB;
+ data->hw_resource.type = IFX_RSC_SCB;
data->hw_resource.block_num = ifx_cat1_uart_get_hw_block_num(config->reg_addr);
/* Configure dt provided device signals when available */
@@ -803,7 +804,7 @@
#endif
#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
-#define PERI_INFO(n) .clock_peri_group = DT_PROP_BY_IDX(DT_INST_PHANDLE(n, clocks), clk_dst, 1),
+#define PERI_INFO(n) .clock_peri_group = DT_PROP_BY_IDX(DT_INST_PHANDLE(n, clocks), peri_group, 1),
#else
#define PERI_INFO(n)
#endif
@@ -829,9 +830,9 @@
.clock = \
{ \
.block = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
- DT_PROP_BY_IDX(DT_INST_PHANDLE(n, clocks), clk_dst, 1), \
+ DT_PROP_BY_IDX(DT_INST_PHANDLE(n, clocks), peri_group, 1), \
DT_INST_PROP_BY_PHANDLE(n, clocks, div_type)), \
- .channel = DT_INST_PROP_BY_PHANDLE(n, clocks, div_num), \
+ .channel = DT_INST_PROP_BY_PHANDLE(n, clocks, channel), \
}, \
PERI_INFO(n)
diff --git a/dts/arm/infineon/cat1b/psc3/system_clocks.dtsi b/dts/arm/infineon/cat1b/psc3/system_clocks.dtsi
index 89b02d5..10338b5 100644
--- a/dts/arm/infineon/cat1b/psc3/system_clocks.dtsi
+++ b/dts/arm/infineon/cat1b/psc3/system_clocks.dtsi
@@ -10,7 +10,8 @@
#define DIV_16_5_BIT 02
#define DIV_24_5_BIT 03
-#include <dt-bindings/clock/ifx_clock_source_def.h>
+#include <dt-bindings/clock/ifx_clock_source_common.h>
+#include <dt-bindings/clock/ifx_clock_source_psc3xx.h>
/ {
srss_power: srss_power {
@@ -26,8 +27,7 @@
#clock-cells = <0>;
compatible = "infineon,fixed-clock";
clock-frequency = <48000000>;
- clock-block = <IFX_CAT1_CLOCK_BLOCK_IHO>;
- clock-instance = <0>;
+ system-clock = <IFX_IHO>;
status = "okay";
};
@@ -36,8 +36,7 @@
#clock-cells = <0>;
compatible = "infineon,fixed-clock";
clock-frequency = <8000000>;
- clock-block = <IFX_CAT1_CLOCK_BLOCK_IMO>;
- clock-instance = <0>;
+ system-clock = <IFX_IMO>;
status = "okay";
};
@@ -46,8 +45,7 @@
#clock-cells = <0>;
compatible = "infineon,fixed-clock";
clock-frequency = <96000000>;
- clock-block = <IFX_CAT1_CLOCK_BLOCK_FLL>;
- clock-instance = <0>;
+ system-clock = <IFX_FLL>;
status = "okay";
};
@@ -56,8 +54,8 @@
#clock-cells = <0>;
compatible = "infineon,fixed-factor-clock";
clocks = <&clk_iho>;
- clock-block = <IFX_CAT1_CLOCK_BLOCK_PATHMUX>;
- clock-instance = <0>;
+ system-clock = <IFX_PATHMUX>;
+ instance = <0>;
source-path = <IFX_CAT1_CLKPATH_IN_IHO>;
status = "disabled";
};
@@ -67,8 +65,8 @@
#clock-cells = <0>;
compatible = "infineon,fixed-factor-clock";
clocks = <&clk_iho>;
- clock-block = <IFX_CAT1_CLOCK_BLOCK_PATHMUX>;
- clock-instance = <1>;
+ system-clock = <IFX_PATHMUX>;
+ instance = <1>;
source-path = <IFX_CAT1_CLKPATH_IN_IHO>;
status = "disabled";
};
@@ -78,8 +76,8 @@
#clock-cells = <0>;
compatible = "infineon,fixed-factor-clock";
clocks = <&clk_iho>;
- clock-block = <IFX_CAT1_CLOCK_BLOCK_PATHMUX>;
- clock-instance = <2>;
+ system-clock = <IFX_PATHMUX>;
+ instance = <2>;
source-path = <IFX_CAT1_CLKPATH_IN_IHO>;
status = "disabled";
};
@@ -89,8 +87,8 @@
#clock-cells = <0>;
compatible = "infineon,fixed-factor-clock";
clocks = <&clk_iho>;
- clock-block = <IFX_CAT1_CLOCK_BLOCK_PATHMUX>;
- clock-instance = <3>;
+ system-clock = <IFX_PATHMUX>;
+ instance = <3>;
source-path = <IFX_CAT1_CLKPATH_IN_IHO>;
status = "disabled";
};
@@ -99,10 +97,10 @@
clk_hf0: clk_hf0 {
#clock-cells = <0>;
compatible = "infineon,fixed-factor-clock";
- clock-divider = <IFX_CAT1_CLKHF_NO_DIVIDE>;
+ clock-div = <IFX_CLK_HF_NO_DIVIDE>;
clocks = <&path_mux1>;
- clock-block = <IFX_CAT1_CLOCK_BLOCK_HF>;
- clock-instance = <0>;
+ system-clock = <IFX_HF>;
+ instance = <0>;
status = "disabled";
};
@@ -110,10 +108,10 @@
clk_hf1: clk_hf1 {
#clock-cells = <0>;
compatible = "infineon,fixed-factor-clock";
- clock-divider = <IFX_CAT1_CLKHF_NO_DIVIDE>;
+ clock-div = <IFX_CLK_HF_NO_DIVIDE>;
clocks = <&path_mux1>;
- clock-block = <IFX_CAT1_CLOCK_BLOCK_HF>;
- clock-instance = <1>;
+ system-clock = <IFX_HF>;
+ instance = <1>;
status = "disabled";
};
@@ -121,10 +119,10 @@
clk_hf2: clk_hf2 {
#clock-cells = <0>;
compatible = "infineon,fixed-factor-clock";
- clock-divider = <IFX_CAT1_CLKHF_NO_DIVIDE>;
+ clock-div = <IFX_CLK_HF_NO_DIVIDE>;
clocks = <&path_mux0>;
- clock-block = <IFX_CAT1_CLOCK_BLOCK_HF>;
- clock-instance = <2>;
+ system-clock = <IFX_HF>;
+ instance = <2>;
status = "disabled";
};
@@ -132,10 +130,10 @@
clk_hf3: clk_hf3 {
#clock-cells = <0>;
compatible = "infineon,fixed-factor-clock";
- clock-divider = <IFX_CAT1_CLKHF_NO_DIVIDE>;
+ clock-div = <IFX_CLK_HF_NO_DIVIDE>;
clocks = <&path_mux2>;
- clock-block = <IFX_CAT1_CLOCK_BLOCK_HF>;
- clock-instance = <3>;
+ system-clock = <IFX_HF>;
+ instance = <3>;
status = "disabled";
};
@@ -143,10 +141,10 @@
clk_hf4: clk_hf4 {
#clock-cells = <0>;
compatible = "infineon,fixed-factor-clock";
- clock-divider = <IFX_CAT1_CLKHF_NO_DIVIDE>;
+ clock-div = <IFX_CLK_HF_NO_DIVIDE>;
clocks = <&path_mux0>;
- clock-block = <IFX_CAT1_CLOCK_BLOCK_HF>;
- clock-instance = <4>;
+ system-clock = <IFX_HF>;
+ instance = <4>;
status = "disabled";
};
};
@@ -156,11 +154,11 @@
/* 24.5-bit */
peri0_group0_24_5bit_0: peri0_group0_24_5bit_0 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 00]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 00]; /* inst#, group# */
div-type = <DIV_24_5_BIT>;
- div-num = <0>;
- div-value = <1>;
+ channel = <0>;
+ clock-div = <1>;
status = "disabled";
};
@@ -168,11 +166,11 @@
/* 8-bit */
peri0_group1_8bit_0: peri0_group1_8bit_0 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 01]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 01]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <0>;
- div-value = <1>;
+ channel = <0>;
+ clock-div = <1>;
status = "disabled";
};
@@ -180,74 +178,74 @@
/* 8-bit */
peri0_group4_8bit_0: peri0_group4_8bit_0 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 04]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 04]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <0>;
- div-value = <1>;
+ channel = <0>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group4_8bit_1: peri0_group4_8bit_1 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 04]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 04]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <1>;
- div-value = <1>;
+ channel = <1>;
+ clock-div = <1>;
status = "disabled";
};
/* 16-bit */
peri0_group4_16bit_0: peri0_group4_16bit_0 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 04]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 04]; /* inst#, group# */
div-type = <DIV_16_BIT>;
- div-num = <0>;
- div-value = <1>;
+ channel = <0>;
+ clock-div = <1>;
status = "disabled";
};
/* 16.5-bit */
peri0_group4_16_5bit_0: peri0_group4_16_5bit_0 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 04]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 04]; /* inst#, group# */
div-type = <DIV_16_5_BIT>;
- div-num = <0>;
- div-value = <1>;
+ channel = <0>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group4_16_5bit_1: peri0_group4_16_5bit_1 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 04]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 04]; /* inst#, group# */
div-type = <DIV_16_5_BIT>;
- div-num = <1>;
- div-value = <1>;
+ channel = <1>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group4_16_5bit_2: peri0_group4_16_5bit_2 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 04]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 04]; /* inst#, group# */
div-type = <DIV_16_5_BIT>;
- div-num = <2>;
- div-value = <1>;
+ channel = <2>;
+ clock-div = <1>;
status = "disabled";
};
/* 24.5-bit */
peri0_group4_24_5bit_0: peri0_group4_24_5bit_0 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 04]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 04]; /* inst#, group# */
div-type = <DIV_24_5_BIT>;
- div-num = <0>;
- div-value = <1>;
+ channel = <0>;
+ clock-div = <1>;
status = "disabled";
};
@@ -255,142 +253,142 @@
/* 8-bit */
peri0_group5_8bit_0: peri0_group5_8bit_0 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <0>;
- div-value = <1>;
+ channel = <0>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group5_8bit_1: peri0_group5_8bit_1 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <1>;
- div-value = <1>;
+ channel = <1>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group5_8bit_2: peri0_group5_8bit_2 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <2>;
- div-value = <1>;
+ channel = <2>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group5_8bit_3: peri0_group5_8bit_3 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <3>;
- div-value = <1>;
+ channel = <3>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group5_8bit_4: peri0_group5_8bit_4 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <4>;
- div-value = <1>;
+ channel = <4>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group5_8bit_5: peri0_group5_8bit_5 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <5>;
- div-value = <1>;
+ channel = <5>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group5_8bit_6: peri0_group5_8bit_6 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <6>;
- div-value = <1>;
+ channel = <6>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group5_8bit_7: peri0_group5_8bit_7 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <7>;
- div-value = <1>;
+ channel = <7>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group5_8bit_8: peri0_group5_8bit_8 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <8>;
- div-value = <1>;
+ channel = <8>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group5_8bit_9: peri0_group5_8bit_9 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_8_BIT>;
- div-num = <9>;
- div-value = <1>;
+ channel = <9>;
+ clock-div = <1>;
status = "disabled";
};
/* 16-bit */
peri0_group5_16bit_0: peri0_group5_16bit_0 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_16_BIT>;
- div-num = <0>;
- div-value = <1>;
+ channel = <0>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group5_16bit_1: peri0_group5_16bit_1 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_16_BIT>;
- div-num = <1>;
- div-value = <1>;
+ channel = <1>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group5_16bit_2: peri0_group5_16bit_2 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_16_BIT>;
- div-num = <2>;
- div-value = <1>;
+ channel = <2>;
+ clock-div = <1>;
status = "disabled";
};
peri0_group5_16bit_3: peri0_group5_16bit_3 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 05]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 05]; /* inst#, group# */
div-type = <DIV_16_BIT>;
- div-num = <3>;
- div-value = <1>;
+ channel = <3>;
+ clock-div = <1>;
status = "disabled";
};
@@ -398,11 +396,11 @@
/* 16.5-bit */
peri0_group6_16_5bit_0: peri0_group6_16_5bit_0 {
#clock-cells = <0>;
- compatible = "infineon,cat1-peri-div";
- clk-dst = [00 06]; /* inst#, group# */
+ compatible = "infineon,peri-div";
+ peri-group = [00 06]; /* inst#, group# */
div-type = <DIV_16_5_BIT>;
- div-num = <0>;
- div-value = <1>;
+ channel = <0>;
+ clock-div = <1>;
status = "disabled";
};
};
diff --git a/dts/bindings/clock/infineon,fixed-clock.yaml b/dts/bindings/clock/infineon,fixed-clock.yaml
index 0c25ef7..129d6cb 100644
--- a/dts/bindings/clock/infineon,fixed-clock.yaml
+++ b/dts/bindings/clock/infineon,fixed-clock.yaml
@@ -7,23 +7,13 @@
compatible: "infineon,fixed-clock"
-include: [base.yaml, clock-controller.yaml]
+include: fixed-clock.yaml
properties:
- clock-frequency:
+ system-clock:
type: int
- description: output clock frequency (Hz)
required: true
-
- clock-block:
- type: int
- description: Clock HW block number (refer to ifx_cat1_clock_block in clock_control_ifx_cat1.h)
- required: true
-
- clock-instance:
- type: int
- description: TEMP
- required: true
-
- "#clock-cells":
- const: 0
+ description: |
+ The type of clock (refer to include/.../dt-bindings/clock/ifx_clock_source_common.h):
+ clk_iho : system-clock = <IFX_IHO>
+ clk_pilo : system-clock = <IFX_PILO>
diff --git a/dts/bindings/clock/infineon,fixed-factor-clock.yaml b/dts/bindings/clock/infineon,fixed-factor-clock.yaml
index b926f24..f540459 100644
--- a/dts/bindings/clock/infineon,fixed-factor-clock.yaml
+++ b/dts/bindings/clock/infineon,fixed-factor-clock.yaml
@@ -7,30 +7,25 @@
compatible: "infineon,fixed-factor-clock"
-include: [base.yaml, clock-controller.yaml]
+include: fixed-factor-clock.yaml
properties:
- clocks:
- type: phandle-array
- description: input clock source
-
- clock-block:
+ system-clock:
type: int
- description: Clock HW block number (refer to ifx_cat1_clock_block in clock_control_ifx_cat1.h)
required: true
+ description: |
+ The type of clock (refer to include/.../dt-bindings/clock/ifx_clock_source_common.h):
+ path_mux5 : system-clock = <IFX_PATHMUX>
+ clk_hf0 : system-clock = <IFX_HF>
- clock-instance:
+ instance:
type: int
- description: TEMP
required: true
-
- clock-divider:
- type: int
- description: TEMP
+ description: |
+ Instance of a given clock type.
+ path_mux5 : instance = <5>
+ clk_hf0 : instance = <0>
source-path:
type: int
- description: TEMP
-
- "#clock-cells":
- const: 0
+ description: Path that indicates source clock.
diff --git a/dts/bindings/clock/infineon,peri-div.yaml b/dts/bindings/clock/infineon,peri-div.yaml
index c6c6e4e..4b55806 100644
--- a/dts/bindings/clock/infineon,peri-div.yaml
+++ b/dts/bindings/clock/infineon,peri-div.yaml
@@ -1,31 +1,33 @@
-# Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
-# an affiliate of Cypress Semiconductor Corporation
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
#
# SPDX-License-Identifier: Apache-2.0
-description: infineon cat1 peripheral divider 8bit.
+description: infineon peripheral divider
-compatible: "infineon,cat1-peri-div"
+compatible: "infineon,peri-div"
include: [clock-controller.yaml, base.yaml]
properties:
- clk-dst:
+ peri-group:
type: uint8-array
description: |
- Clock Connections. PDL uses the target IP to identify the peri group
+ Peri instance and group of given peripheral divider:
+ peri0_group1_... : peri-group = [00 01]
+ peri1_group3_... : peri-group = [01 03]
div-type:
type: int
description: |
- Clock divider type.
+ Programmable clock divider types: DIV_8_BIT, DIV_16_BIT, DIV_16_5_BIT, DIV_24_5_BIT
- div-num:
+ channel:
type: int
description: |
- Programmable clock divider types: DIV_8_BIT, DIV_16_BIT, DIV_16_5_BIT, DIV_24_5_BIT
+ Channel of given peripheral divider.
- div-value:
+ clock-div:
type: int
description: |
For non-fractional clock dividers (div-type: DIV_8_BIT, DIV_16_BIT)
@@ -45,11 +47,19 @@
it divides the clock by 1/32 for each count. To divide the clock by 11/32nds
set this value to 11.
- scb-block:
+ resource-type:
type: int
required: true
description: |
- SCB device instance peripheral clock is assigned to:
- &scb0 : scb-block = <0>
- &scb3 : scb-block = <3>
- &scb5 : scb-block = <5>
+ Resource type that the peripheral clock is assigned to:
+ &scb3 : resource-type = IFX_RSC_SCB
+ &tcpwm0_0 : resource-type = IFX_RSC_TCPWM
+
+ resource-instance:
+ type: int
+ required: true
+ description: |
+ Resource instance that the peripheral clock is assigned to:
+ &scb0 : resource-instance = <0>
+ &scb3 : resource-instance = <3>
+ &scb5 : resource-instance = <5>
diff --git a/include/zephyr/drivers/clock_control/clock_control_ifx_cat1.h b/include/zephyr/drivers/clock_control/clock_control_ifx_cat1.h
index 7b0da7a..8726743 100644
--- a/include/zephyr/drivers/clock_control/clock_control_ifx_cat1.h
+++ b/include/zephyr/drivers/clock_control/clock_control_ifx_cat1.h
@@ -10,6 +10,7 @@
#define IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block) ((cy_en_divider_types_t)((block) & 0x03))
+#if !defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
/* Converts the group/div pair into a unique block number. */
#define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(group, div) (((group) << 2) | (div))
@@ -22,41 +23,25 @@
(gr), CY_SYSCLK_DIV_16_5_BIT), /*!< 16.5bit Peripheral Divider Group */ \
IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_24_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
(gr), CY_SYSCLK_DIV_24_5_BIT) /*!< 24.5bit Peripheral Divider Group */
+#else
+/* Converts the group/div pair into a unique block number. */
+#define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(instance, group, div) \
+ (((group + (instance * PERI0_PERI_PCLK_PCLK_GROUP_NR)) << 2) | (div))
+#define IFX_CAT1_PERIPHERAL_CLOCK_GET_INSTANCE(clock) ((clock >> 2) / PERI0_PERI_PCLK_PCLK_GROUP_NR)
+#define IFX_CAT1_PERIPHERAL_CLOCK_GET_GROUP(clock) \
+ ((clock >> 2) - \
+ (IFX_CAT1_PERIPHERAL_CLOCK_GET_INSTANCE(clock) * PERI0_PERI_PCLK_PCLK_GROUP_NR))
-enum ifx_cat1_resource {
- IFX_CAT1_RSC_ADC, /*!< Analog to digital converter */
- IFX_CAT1_RSC_ADCMIC, /*!< Analog to digital converter with Analog Mic support */
- IFX_CAT1_RSC_BLESS, /*!< Bluetooth communications block */
- IFX_CAT1_RSC_CAN, /*!< CAN communication block */
- IFX_CAT1_RSC_CLKPATH, /*!< Clock Path. DEPRECATED. */
- IFX_CAT1_RSC_CLOCK, /*!< Clock */
- IFX_CAT1_RSC_CRYPTO, /*!< Crypto hardware accelerator */
- IFX_CAT1_RSC_DAC, /*!< Digital to analog converter */
- IFX_CAT1_RSC_DMA, /*!< DMA controller */
- IFX_CAT1_RSC_DW, /*!< Datawire DMA controller */
- IFX_CAT1_RSC_ETH, /*!< Ethernet communications block */
- IFX_CAT1_RSC_GPIO, /*!< General purpose I/O pin */
- IFX_CAT1_RSC_I2S, /*!< I2S communications block */
- IFX_CAT1_RSC_I3C, /*!< I3C communications block */
- IFX_CAT1_RSC_KEYSCAN, /*!< KeyScan block */
- IFX_CAT1_RSC_LCD, /*!< Segment LCD controller */
- IFX_CAT1_RSC_LIN, /*!< LIN communications block */
- IFX_CAT1_RSC_LPCOMP, /*!< Low power comparator */
- IFX_CAT1_RSC_LPTIMER, /*!< Low power timer */
- IFX_CAT1_RSC_OPAMP, /*!< Opamp */
- IFX_CAT1_RSC_PDM, /*!< PCM/PDM communications block */
- IFX_CAT1_RSC_PTC, /*!< Programmable Threshold comparator */
- IFX_CAT1_RSC_SMIF, /*!< Quad-SPI communications block */
- IFX_CAT1_RSC_RTC, /*!< Real time clock */
- IFX_CAT1_RSC_SCB, /*!< Serial Communications Block */
- IFX_CAT1_RSC_SDHC, /*!< SD Host Controller */
- IFX_CAT1_RSC_SDIODEV, /*!< SDIO Device Block */
- IFX_CAT1_RSC_TCPWM, /*!< Timer/Counter/PWM block */
- IFX_CAT1_RSC_TDM, /*!< TDM block */
- IFX_CAT1_RSC_UDB, /*!< UDB Array */
- IFX_CAT1_RSC_USB, /*!< USB communication block */
- IFX_CAT1_RSC_INVALID, /*!< Placeholder for invalid type */
-};
+#define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(instance, gr) \
+ IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_8BIT = \
+ IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_8_BIT), \
+ IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16BIT = \
+ IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_BIT), \
+ IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16_5BIT = \
+ IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_5_BIT), \
+ IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_24_5BIT = \
+ IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_24_5_BIT)
+#endif
enum ifx_cat1_clock_block {
#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1A)
@@ -280,6 +265,94 @@
IFX_CAT1_CLOCK_BLOCK_SLOW, /*!< Slow Clock for CM0+ */
IFX_CAT1_CLOCK_BLOCK_MEM, /*!< CLK MEM */
IFX_CAT1_CLOCK_BLOCK_TIMER, /*!< CLK Timer */
+#elif defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
+
+ IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
+ CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_8_BIT */
+ IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
+ CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_BIT */
+ IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
+ CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT
+ */
+ IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
+ CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT
+ */
+
+#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 1)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 0),
+#endif
+#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 2)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 1),
+#endif
+#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 3)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 2),
+#endif
+#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 4)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 3),
+#endif
+#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 5)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 4),
+#endif
+#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 6)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 5),
+#endif
+#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 7)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 6),
+#endif
+#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 8)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 7),
+#endif
+#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 9)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 8),
+#endif
+#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 10)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 9),
+#endif
+#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 11)
+#warning "Unhandled PERI0 PCLK number"
+#endif
+
+#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 1)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 0),
+#endif
+#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 2)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 1),
+#endif
+#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 3)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 2),
+#endif
+#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 4)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 3),
+#endif
+#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 5)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 4),
+#endif
+#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 6)
+ IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 5),
+#endif
+#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 7)
+#warning "Unhandled PERI1 PCLK number"
+#endif
+
+ IFX_CAT1_CLOCK_BLOCK_IHO, /*!< Internal High Speed Oscillator Input Clock */
+ IFX_CAT1_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */
+ IFX_CAT1_CLOCK_BLOCK_EXT, /*!< External Input Clock */
+ IFX_CAT1_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */
+ IFX_CAT1_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */
+
+ IFX_CAT1_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */
+
+ IFX_CAT1_CLOCK_BLOCK_DPLL250, /*!< 250MHz Digital Phase-Locked Loop Clock */
+ IFX_CAT1_CLOCK_BLOCK_DPLL500, /*!< 500MHz Digital Phase-Locked Loop Clock */
+ IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER, /*!< ECO Prescaler Divider */
+
+ IFX_CAT1_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */
+ IFX_CAT1_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */
+ IFX_CAT1_CLOCK_BLOCK_HF, /*!< High Frequency Clock */
+
+ IFX_CAT1_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */
+ IFX_CAT1_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */
+
#endif
};
@@ -291,8 +364,8 @@
};
struct ifx_cat1_resource_inst {
- enum ifx_cat1_resource type; /* !< The resource block type */
- uint8_t block_num; /* !< The resource block index */
+ uint8_t type; /* !< The resource block type */
+ uint8_t block_num; /* !< The resource block index */
/**
* The channel number, if the resource type defines multiple channels
* per block instance. Otherwise, 0
@@ -307,7 +380,7 @@
static inline cy_rslt_t ifx_cat1_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest,
const struct ifx_cat1_clock *_clock)
{
-#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
+#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
return Cy_SysClk_PeriPclkEnableDivider(
clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
_clock->channel);
@@ -322,7 +395,7 @@
const struct ifx_cat1_clock *_clock,
uint32_t div)
{
-#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
+#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
return Cy_SysClk_PeriPclkSetDivider(
clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
_clock->channel, div);
@@ -338,7 +411,7 @@
const struct ifx_cat1_clock *_clock, uint32_t div_int,
uint32_t div_frac)
{
-#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
+#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
return Cy_SysClk_PeriPclkSetFracDivider(
clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
_clock->channel, div_int, div_frac);
@@ -353,7 +426,7 @@
static inline cy_rslt_t ifx_cat1_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest,
const struct ifx_cat1_clock *_clock)
{
-#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
+#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
return Cy_SysClk_PeriPclkAssignDivider(
clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
_clock->channel);
diff --git a/include/zephyr/dt-bindings/clock/ifx_clock_source_boards.h b/include/zephyr/dt-bindings/clock/ifx_clock_source_boards.h
new file mode 100644
index 0000000..057764a
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/ifx_clock_source_boards.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if defined(CONFIG_SOC_SERIES_PSE84)
+#include "ifx_clock_source_pse8xx.h"
+#elif defined(CONFIG_SOC_SERIES_PSC3)
+#include "ifx_clock_source_psc3xx.h"
+#endif
diff --git a/include/zephyr/dt-bindings/clock/ifx_clock_source_common.h b/include/zephyr/dt-bindings/clock/ifx_clock_source_common.h
index 01f8ed0..5e60871 100644
--- a/include/zephyr/dt-bindings/clock/ifx_clock_source_common.h
+++ b/include/zephyr/dt-bindings/clock/ifx_clock_source_common.h
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
- * an affiliate of Cypress Semiconductor Corporation
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,74 +8,80 @@
#define CLK_SOURCE_IHO
#define CLK_SOURCE_PILO
-#define IFX_CAT1_CLOCK_BLOCK_IHO 1 /*!< Internal High Speed Oscillator Input Clock */
-#define IFX_CAT1_CLOCK_BLOCK_IMO 2 /*!< Internal Main Oscillator Input Clock */
-#define IFX_CAT1_CLOCK_BLOCK_ECO 3 /*!< External Crystal Oscillator Input Clock */
-#define IFX_CAT1_CLOCK_BLOCK_EXT 4 /*!< External Input Clock */
-#define IFX_CAT1_CLOCK_BLOCK_ALTHF 5 /*!< Alternate High Frequency Input Clock */
-#define IFX_CAT1_CLOCK_BLOCK_ALTLF 6 /*!< Alternate Low Frequency Input Clock */
-#define IFX_CAT1_CLOCK_BLOCK_ILO 7 /*!< Internal Low Speed Oscillator Input Clock */
-#define IFX_CAT1_CLOCK_BLOCK_PILO 8 /*!< Precision ILO Input Clock */
-#define IFX_CAT1_CLOCK_BLOCK_WCO 9 /*!< Watch Crystal Oscillator Input Clock */
-#define IFX_CAT1_CLOCK_BLOCK_MFO 10 /*!< Medium Frequency Oscillator Clock */
+#define IFX_IHO 1 /*!< Internal High Speed Oscillator Input Clock */
+#define IFX_IMO 2 /*!< Internal Main Oscillator Input Clock */
+#define IFX_ECO 3 /*!< External Crystal Oscillator Input Clock */
+#define IFX_EXT 4 /*!< External Input Clock */
+#define IFX_ALTHF 5 /*!< Alternate High Frequency Input Clock */
+#define IFX_ALTLF 6 /*!< Alternate Low Frequency Input Clock */
+#define IFX_ILO 7 /*!< Internal Low Speed Oscillator Input Clock */
+#define IFX_PILO 8 /*!< Precision ILO Input Clock */
+#define IFX_WCO 9 /*!< Watch Crystal Oscillator Input Clock */
+#define IFX_MFO 10 /*!< Medium Frequency Oscillator Clock */
+#define IFX_PATHMUX 11 /*!< Path selection mux for input to FLL/PLLs */
+#define IFX_FLL 12 /*!< Frequency-Locked Loop Clock */
+#define IFX_PLL200 13 /*!< 200MHz Phase-Locked Loop Clock */
+#define IFX_PLL400 14 /*!< 400MHz Phase-Locked Loop Clock */
+#define IFX_ECO_PRESCALER 15 /*!< ECO Prescaler Divider */
+#define IFX_LF 16 /*!< Low Frequency Clock */
+#define IFX_MF 17 /*!< Medium Frequency Clock */
+#define IFX_HF 18 /*!< High Frequency Clock */
+#define IFX_PUMP 19 /*!< Analog Pump Clock */
+#define IFX_BAK 20 /*!< Backup Power Domain Clock */
+#define IFX_ALT_SYS_TICK 21 /*!< Alternative SysTick Clock */
+#define IFX_PERI 22 /*!< Peripheral Clock Group */
+#define IFX_DPLL250_0 23 /*!< 250MHz Digital Phase-Locked Loop Clock 0 */
+#define IFX_DPLL250_1 24 /*!< 250MHz Digital Phase-Locked Loop Clock 1 */
+#define IFX_DPLL500 25 /*!< 500MHz Digital Phase-Locked Loop Clock */
-#define IFX_CAT1_CLOCK_BLOCK_PATHMUX 11 /*!< Path selection mux for input to FLL/PLLs */
+#define IFX_CLK_HF_NO_DIVIDE 0 /**< don't divide clkHf */
+#define IFX_CLK_HF_DIVIDE_BY_2 1 /**< divide clkHf by 2 */
+#define IFX_CLK_HF_DIVIDE_BY_3 2 /**< divide clkHf by 3 */
+#define IFX_CLK_HF_DIVIDE_BY_4 3 /**< divide clkHf by 4 */
+#define IFX_CLK_HF_DIVIDE_BY_5 4 /**< divide clkHf by 5 */
+#define IFX_CLK_HF_DIVIDE_BY_6 5 /**< divide clkHf by 6 */
+#define IFX_CLK_HF_DIVIDE_BY_7 6 /**< divide clkHf by 7 */
+#define IFX_CLK_HF_DIVIDE_BY_8 7 /**< divide clkHf by 8 */
+#define IFX_CLK_HF_DIVIDE_BY_9 8 /**< divide clkHf by 9 */
+#define IFX_CLK_HF_DIVIDE_BY_10 9 /**< divide clkHf by 10 */
+#define IFX_CLK_HF_DIVIDE_BY_11 10 /**< divide clkHf by 11 */
+#define IFX_CLK_HF_DIVIDE_BY_12 11 /**< divide clkHf by 12 */
+#define IFX_CLK_HF_DIVIDE_BY_13 12 /**< divide clkHf by 13 */
+#define IFX_CLK_HF_DIVIDE_BY_14 13 /**< divide clkHf by 14 */
+#define IFX_CLK_HF_DIVIDE_BY_15 14 /**< divide clkHf by 15 */
+#define IFX_CLK_HF_DIVIDE_BY_16 15 /**< divide clkHf by 16 */
+#define IFX_CLK_HF_MAX_DIVIDER /**< Max divider */
-#define IFX_CAT1_CLOCK_BLOCK_FLL 12 /*!< Frequency-Locked Loop Clock */
-#define IFX_CAT1_CLOCK_BLOCK_PLL200 13 /*!< 200MHz Phase-Locked Loop Clock */
-#define IFX_CAT1_CLOCK_BLOCK_PLL400 14 /*!< 400MHz Phase-Locked Loop Clock */
-#define IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER 15 /*!< ECO Prescaler Divider */
-
-#define IFX_CAT1_CLOCK_BLOCK_LF 16 /*!< Low Frequency Clock */
-#define IFX_CAT1_CLOCK_BLOCK_MF 17 /*!< Medium Frequency Clock */
-#define IFX_CAT1_CLOCK_BLOCK_HF 18 /*!< High Frequency Clock */
-
-#define IFX_CAT1_CLOCK_BLOCK_PUMP 19 /*!< Analog Pump Clock */
-#define IFX_CAT1_CLOCK_BLOCK_BAK 20 /*!< Backup Power Domain Clock */
-#define IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK 21 /*!< Alternative SysTick Clock */
-#define IFX_CAT1_CLOCK_BLOCK_PERI 22 /*!< Peripheral Clock Group */
-
-#define IFX_CAT1_CLKHF_NO_DIVIDE 0 /**< don't divide clkHf */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_2 1 /**< divide clkHf by 2 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_3 2 /**< divide clkHf by 3 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_4 3 /**< divide clkHf by 4 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_5 4 /**< divide clkHf by 5 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_6 5 /**< divide clkHf by 6 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_7 6 /**< divide clkHf by 7 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_8 7 /**< divide clkHf by 8 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_9 8 /**< divide clkHf by 9 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_10 9 /**< divide clkHf by 10 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_11 10 /**< divide clkHf by 11 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_12 11 /**< divide clkHf by 12 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_13 12 /**< divide clkHf by 13 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_14 13 /**< divide clkHf by 14 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_15 14 /**< divide clkHf by 15 */
-#define IFX_CAT1_CLKHF_DIVIDE_BY_16 15 /**< divide clkHf by 16 */
-#define IFX_CAT1_CLKHF_MAX_DIVIDER /**< Max divider */
-
-#define IFX_CAT1_CLKPATH_IN_IMO 0 /**< Select the IMO as the output of the path mux */
-#define IFX_CAT1_CLKPATH_IN_EXT 1 /**< Select the EXT as the output of the path mux */
-#define IFX_CAT1_CLKPATH_IN_ECO 2 /**< Select the ECO as the output of the path mux */
-#define IFX_CAT1_CLKPATH_IN_ALTHF 3 /**< Select the ALTHF as the output of the path mux */
-/* Select the DSI MUX output as the output of the path mux */
-#define IFX_CAT1_CLKPATH_IN_DSIMUX 4
-#define IFX_CAT1_CLKPATH_IN_LPECO 5 /**< Select the LPECO as the output of the path mux */
-#define IFX_CAT1_CLKPATH_IN_IHO 6 /**< Select the IHO as the output of the path mux */
-/* Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. \
- * Make sure the DSI clock sources are available on used device. \
- */
-#define IFX_CAT1_CLKPATH_IN_DSI 0x100
-/**< Select the ILO (16) as the output of the DSI mux and path mux */
-#define IFX_CAT1_CLKPATH_IN_ILO 0x110
-/**< Select the WCO (17) as the output of the DSI mux and path mux */
-#define IFX_CAT1_CLKPATH_IN_WCO 0x111
-/**< Select the ALTLF (18) as the output of the DSI mux and path mux. \
- * Make sure the ALTLF clock sources in available on used device. \
- */
-#define IFX_CAT1_CLKPATH_IN_ALTLF 0x112
-/**< Select the PILO (19) as the output of the DSI mux and path mux. \
- * Make sure the PILO clock sources in available on used device. \
- */
-#define IFX_CAT1_CLKPATH_IN_PILO 0x113
-/**< Select the ILO1 (20) as the output of the DSI mux and path mux */
-#define IFX_CAT1_CLKPATH_IN_ILO1 0x114
+/* Target resource types for peripheral dividers */
+#define IFX_RSC_ADC 0 /*!< Analog to digital converter */
+#define IFX_RSC_ADCMIC 1 /*!< Analog to digital converter with Analog Mic support */
+#define IFX_RSC_BLESS 2 /*!< Bluetooth communications block */
+#define IFX_RSC_CAN 3 /*!< CAN communication block */
+#define IFX_RSC_CLKPATH 4 /*!< Clock Path. DEPRECATED. */
+#define IFX_RSC_CLOCK 5 /*!< Clock */
+#define IFX_RSC_CRYPTO 6 /*!< Crypto hardware accelerator */
+#define IFX_RSC_DAC 7 /*!< Digital to analog converter */
+#define IFX_RSC_DMA 8 /*!< DMA controller */
+#define IFX_RSC_DW 9 /*!< Datawire DMA controller */
+#define IFX_RSC_ETH 10 /*!< Ethernet communications block */
+#define IFX_RSC_GPIO 11 /*!< General purpose I/O pin */
+#define IFX_RSC_I2S 12 /*!< I2S communications block */
+#define IFX_RSC_I3C 13 /*!< I3C communications block */
+#define IFX_RSC_KEYSCAN 14 /*!< KeyScan block */
+#define IFX_RSC_LCD 15 /*!< Segment LCD controller */
+#define IFX_RSC_LIN 16 /*!< LIN communications block */
+#define IFX_RSC_LPCOMP 17 /*!< Low power comparator */
+#define IFX_RSC_LPTIMER 18 /*!< Low power timer */
+#define IFX_RSC_OPAMP 19 /*!< Opamp */
+#define IFX_RSC_PDM 20 /*!< PCM/PDM communications block */
+#define IFX_RSC_PTC 21 /*!< Programmable Threshold comparator */
+#define IFX_RSC_SMIF 22 /*!< Quad-SPI communications block */
+#define IFX_RSC_RTC 23 /*!< Real time clock */
+#define IFX_RSC_SCB 24 /*!< Serial Communications Block */
+#define IFX_RSC_SDHC 25 /*!< SD Host Controller */
+#define IFX_RSC_SDIODEV 26 /*!< SDIO Device Block */
+#define IFX_RSC_TCPWM 27 /*!< Timer/Counter/PWM block */
+#define IFX_RSC_TDM 28 /*!< TDM block */
+#define IFX_RSC_UDB 29 /*!< UDB Array */
+#define IFX_RSC_USB 30 /*!< USB communication block */
+#define IFX_RSC_INVALID 31 /*!< Placeholder for invalid type */
diff --git a/include/zephyr/dt-bindings/clock/ifx_clock_source_psc3xx.h b/include/zephyr/dt-bindings/clock/ifx_clock_source_psc3xx.h
new file mode 100644
index 0000000..7fec373
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/ifx_clock_source_psc3xx.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define IFX_CAT1_CLKPATH_IN_IMO 0 /**< Select the IMO as the output of the path mux */
+#define IFX_CAT1_CLKPATH_IN_EXT 1 /**< Select the EXT as the output of the path mux */
+#define IFX_CAT1_CLKPATH_IN_ECO 2 /**< Select the ECO as the output of the path mux */
+#define IFX_CAT1_CLKPATH_IN_ALTHF 3 /**< Select the ALTHF as the output of the path mux */
+/* Select the DSI MUX output as the output of the path mux */
+#define IFX_CAT1_CLKPATH_IN_DSIMUX 4
+#define IFX_CAT1_CLKPATH_IN_LPECO 5 /**< Select the LPECO as the output of the path mux */
+#define IFX_CAT1_CLKPATH_IN_IHO 6 /**< Select the IHO as the output of the path mux */
+/* Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. \
+ * Make sure the DSI clock sources are available on used device. \
+ */
+#define IFX_CAT1_CLKPATH_IN_DSI 0x100
+/**< Select the ILO (16) as the output of the DSI mux and path mux */
+#define IFX_CAT1_CLKPATH_IN_ILO 0x110
+/**< Select the WCO (17) as the output of the DSI mux and path mux */
+#define IFX_CAT1_CLKPATH_IN_WCO 0x111
+/**< Select the ALTLF (18) as the output of the DSI mux and path mux. \
+ * Make sure the ALTLF clock sources in available on used device. \
+ */
+#define IFX_CAT1_CLKPATH_IN_ALTLF 0x112
+/**< Select the PILO (19) as the output of the DSI mux and path mux. \
+ * Make sure the PILO clock sources in available on used device. \
+ */
+#define IFX_CAT1_CLKPATH_IN_PILO 0x113
+/**< Select the ILO1 (20) as the output of the DSI mux and path mux */
+#define IFX_CAT1_CLKPATH_IN_ILO1 0x114
diff --git a/include/zephyr/dt-bindings/clock/ifx_clock_source_pse8xx.h b/include/zephyr/dt-bindings/clock/ifx_clock_source_pse8xx.h
new file mode 100644
index 0000000..94cccf6
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/ifx_clock_source_pse8xx.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Select the IHO as the output of the path mux */
+#define IFX_CAT1_CLKPATH_IN_IHO 0
+
+/* Select the EXT as the output of the path mux */
+#define IFX_CAT1_CLKPATH_IN_EXT 1
+
+/* Select the ECO as the output of the path mux */
+#define IFX_CAT1_CLKPATH_IN_ECO 2
+
+/* Select the IMO as the output of the path mux */
+#define IFX_CAT1_CLKPATH_IN_IMO 3
+
+/* Select the ALTHF0 as the output of the path mux */
+#define IFX_CAT1_CLKPATH_IN_ALTHF0 4
+
+/* Select the ALTHF1 as the output of the path mux */
+#define IFX_CAT1_CLKPATH_IN_ALTHF1 5
+
+/* Select the DSI MUX output as the output of the path mux */
+#define IFX_CAT1_CLKPATH_IN_DSIMUX 7
+
+/* Select a DSI signal (0 - 15) as the output of the DSI mux and path mux.
+ * Make sure the DSI clock sources are available on used device.
+ */
+#define IFX_CAT1_CLKPATH_IN_DSI 0x100
+
+/* Select the ILO (16) as the output of the DSI mux and path mux */
+#define IFX_CAT1_CLKPATH_IN_ILO 0x110
+
+/* Select the WCO (17) as the output of the DSI mux and path mux */
+#define IFX_CAT1_CLKPATH_IN_WCO 0x111
+
+/* Select the ALTLF (18) as the output of the DSI mux and path mux.
+ * Make sure the ALTLF clock sources in available on used device.
+ */
+#define IFX_CAT1_CLKPATH_IN_ALTLF 0x112
+
+/* Select the PILO (19) as the output of the DSI mux and path mux.
+ * Make sure the PILO clock sources in available on used device.
+ */
+#define IFX_CAT1_CLKPATH_IN_PILO 0x113
