| commit | 28bb21cfe611f80a248cb7f11b30ec3256b3e620 | [log] [tgz] |
|---|---|---|
| author | Ryan McClelland <ryanmcclelland@meta.com> | Fri Mar 31 12:06:51 2023 -0700 |
| committer | Anas Nashif <anas.nashif@intel.com> | Sat Apr 01 07:37:03 2023 -0400 |
| tree | 70f5fa6ec589ae39aa5529e1861fc1e9bdc75b55 | |
| parent | 3db1e550c831089f0c538241ec50a6a35845d455 [diff] |
drivers: i3c: cdns: set tx fifo threshold interrupt to half the fifo When a controller is running at full SDR speed at 12.5MHz, there needs to be enough time for the processor get around to writing more data in the fifo. Previously at -1 the size, this was enough for 1MHz with a decent processor, but not enough at a 12.5MHz SCL. Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>