| commit | 2de3133a050c649ac052711a5e5262b057a83939 | [log] [tgz] |
|---|---|---|
| author | TOKITA Hiroshi <tokita.hiroshi@gmail.com> | Tue Mar 03 21:27:10 2020 +0900 |
| committer | Carles Cufí <carles.cufi@nordicsemi.no> | Mon Dec 20 17:51:30 2021 +0100 |
| tree | c0622ea892bb721880ec3fe64f0b07ddfae13538 | |
| parent | d79d4f0bea47c51d5c3eddc93e2c7025f1ff9bf4 [diff] |
riscv: Add an option for configuring mcause exception mask GD32V processor core is used non-standard bitmask for mcause register. Add option to configure the bitmask to support GD32V. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>