| commit | 2f40474c146ada6bd625cc291bd67f0d2036658c | [log] [tgz] |
|---|---|---|
| author | Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com> | Thu Mar 14 16:51:51 2024 +0200 |
| committer | Anas Nashif <anas.nashif@intel.com> | Fri Mar 15 06:27:13 2024 -0400 |
| tree | 7d6f447530906fe5b87d3b56ca804f8bec82e223 | |
| parent | ca147ff6376f57378fe2b28f72495849e5c2d8a2 [diff] |
nxp: imx8ulp: correct value of `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` The core clock of 8ULP's HIFI4 DSP runs at 475.2MHz. As such, correct the value of `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` to reflect this. Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>