3112f856d2b21e560570ba36b392408ec5852271 - third_party/github/zephyrproject-rtos/zephyr

commit: 3112f856d2b21e560570ba36b392408ec5852271
[log]
author: Daniel Schultz <dnltz@aesc-silicon.de>
Wed Apr 30 08:06:28 2025 +0200
committer: Benjamin Cabé <kartben@gmail.com>
Wed May 14 14:09:41 2025 +0200
tree: 3ef02cd684fc433d513ff12227701f33affc262b
parent: 14b83d130ddfbf64ecf502ac90b5504591eae44a [diff]

soc: Add aesc

Currently, the only available platform is Nitrogen, featuring a
VexRiscv CPU that boots from external SPI flash and runs code from
external HyperRAM.

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>

soc/aesc/CMakeLists.txt[Added - diff]
soc/aesc/Kconfig[Added - diff]
soc/aesc/Kconfig.defconfig[Added - diff]
soc/aesc/Kconfig.soc[Added - diff]
soc/aesc/ip_identification.h[Added - diff]
soc/aesc/nitrogen/CMakeLists.txt[Added - diff]
soc/aesc/nitrogen/Kconfig[Added - diff]
soc/aesc/nitrogen/Kconfig.defconfig[Added - diff]
soc/aesc/nitrogen/Kconfig.soc[Added - diff]
soc/aesc/nitrogen/linker.ld[Added - diff]
soc/aesc/nitrogen/soc.h[Added - diff]
soc/aesc/soc.yml[Added - diff]

12 files changed