| commit | 317ce524f8661b94ff7029b252f14b33acc8f0c5 | [log] [tgz] |
|---|---|---|
| author | Francois Ramu <francois.ramu@st.com> | Mon Aug 08 10:32:25 2022 +0200 |
| committer | Carles Cufí <carles.cufi@nordicsemi.no> | Wed Aug 10 14:32:14 2022 +0200 |
| tree | 96d1cae34493298241e8baba0fe0cee9dcdfa1b2 | |
| parent | 7edcd8d364469c20395a268598d546e2e1730a48 [diff] |
drivers: clock control: stm32U5 set flash latency before clocks As mentionned here, setting flash latency before any clock setting, and especially before the PLL. Signed-off-by: Francois Ramu <francois.ramu@st.com>