| commit | de684bbdaad72240b4ec2d1ca3359ea5fe5ffe77 | [log] [tgz] |
|---|---|---|
| author | Erwan Gouriou <erwan.gouriou@linaro.org> | Mon Feb 20 10:39:55 2017 +0100 |
| committer | Kumar Gala <kumar.gala@linaro.org> | Wed Feb 22 18:09:22 2017 -0600 |
| tree | b9866b750e6f2e2cb483551afa9aa670f9033cd5 | |
| parent | 0aea7044629e47b186cf0392deff66ffc19cfd90 [diff] |
clock_control: fix to get PLL2 source for PREDV1 working Some fixes where needed to get PLL2 source of PREVI1 functional. Compiled ok with following configuration: CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK=y CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV2=0 CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER=8 Jira: ZEP-1758 Change-Id: I5ddfaef1b44c4c4e5e6adedc158a1c9092bc8df5 Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>