| commit | 5e4e0298e9bb3967b43fed3636de47db2be7182b | [log] [tgz] |
|---|---|---|
| author | Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com> | Thu Feb 11 09:52:29 2021 +0100 |
| committer | Anas Nashif <anas.nashif@intel.com> | Mon Feb 15 09:43:30 2021 -0500 |
| tree | 90cf5248ca712cb2e75fff9a42418ca996b4a5ee | |
| parent | 16c4b65dce533a9e15aa5087f68de60b8b9b305b [diff] |
arch/x86: Generalize cache manipulation functions We assume that all x86 CPUs do have clflush instructions. And the cache line size is now provided through DTS. So detecting clflush instruction as well as the cache line size is no longer required at runtime and thus removed. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>