| commit | 342cbc9e017c76b1aa5ff7e1904c6d7709c99162 | [log] [tgz] |
|---|---|---|
| author | Filip Kokosinski <fkokosinski@internships.antmicro.com> | Thu Mar 28 14:47:16 2019 +0100 |
| committer | Kumar Gala <kumar.gala@gmail.com> | Wed May 15 12:52:16 2019 -0500 |
| tree | 6cea711e9eafa50d27d268eabfdb575327e10f1e | |
| parent | b054517ce712d8e11e2f4df425a052b34aa511e6 [diff] |
soc: riscv32: add LiteX VexRiscV SoC Add LiteX with softcore CPU VexRiscV SoC definitions and default configurations. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>