| commit | 34862656b9e13f7b4b30efaf2d857088d0f0c6cd | [log] [tgz] |
|---|---|---|
| author | Jean-Paul Etienne <fractalclone@gmail.com> | Thu Jun 29 22:45:55 2017 +0200 |
| committer | Anas Nashif <nashif@linux.intel.com> | Fri Jun 30 06:31:51 2017 -0400 |
| tree | 44969eea0b840b7f97788e14b0ead828f4770a6d | |
| parent | a5898da7f5a6e4dc8d3b0b095e6acf7b1f8ff4a6 [diff] |
riscv32: fixed context restore upon exiting ISR By now, t0 register restored value is overwritten by mepc and mstatus values prior to returning from ISR. Fixed by restoring mstatus and mepc registers before restoring the caller-saved registers. As t0 is a temporary register within the riscv ABI, this issue was unnoticed for most applications, except for computation intensive apps, like crypto tests. Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>