3b7221363a6d31993cb40829de3edd2ffffd8b41 - third_party/github/zephyrproject-rtos/zephyr

commit	3b7221363a6d31993cb40829de3edd2ffffd8b41	[log] [tgz]
author	Jim Shu <cwshu@andestech.com>	Thu Jul 29 12:23:19 2021 +0800
committer	Anas Nashif <anas.nashif@intel.com>	Mon Aug 30 13:40:14 2021 -0400
tree	8bd64e11a44deee88ef25a97b55518ae98514ee8
parent	7db0fedcfee49fcc5f7b56c282618cf3700392bb [diff]

soc: riscv: andes_v5: introduce Andes V5 PMA to support nocache memory

Andes V5 PMA can let SW programmably configure memory attribute of
physical memory region. This commit enable CONFIG_NOCACHE_MEMORY of
Andes V5 CPUs based on the PMA. Use PMA region 0 to set whole nocache
section as uncached memory.

Signed-off-by: Jim Shu <cwshu@andestech.com>

soc/riscv/riscv-privilege/andes_v5/CMakeLists.txt[diff]
soc/riscv/riscv-privilege/andes_v5/Kconfig.soc[diff]
soc/riscv/riscv-privilege/andes_v5/ae350/linker.ld[diff]
soc/riscv/riscv-privilege/andes_v5/pma.c[Added - diff]

4 files changed