| commit | 3f8e326d1a63af7eb294c59078a80a3da7f71dfc | [log] [tgz] |
|---|---|---|
| author | Nicolas Pitre <npitre@baylibre.com> | Tue Jun 07 08:04:55 2022 -0400 |
| committer | Anas Nashif <anas.nashif@intel.com> | Thu Jun 23 13:12:05 2022 -0400 |
| tree | dc638c14ea6a4901b94c9f3a0623e01d552a9560 | |
| parent | 95b18c7f9fa3f81b3316b780836336b7cdd7ced1 [diff] |
riscv: stop preserving the tp register needlessly The tp (x4) register is neither caller nor callee saved according to the RISC-V standard calling convention. It only has to be set on thread context switching and is otherwise read-only. To protect the kernel against a possible rogue user thread, the tp is also re-set on exception entry from u-mode. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>