driver: clock: esp32: retrieve HW clock from DTS
ESP32 and ESP32-S2 HW clock are tied to DTS clock configuration.
This changes updates the default configuration to retrieve
this information from DTS.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
diff --git a/boards/xtensa/esp32/esp32_defconfig b/boards/xtensa/esp32/esp32_defconfig
index 924b7f8..099b0c8 100644
--- a/boards/xtensa/esp32/esp32_defconfig
+++ b/boards/xtensa/esp32/esp32_defconfig
@@ -7,8 +7,6 @@
CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
-
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
diff --git a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig b/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig
index 8e04ae5..f5be500 100644
--- a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig
+++ b/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig
@@ -7,8 +7,6 @@
CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
-
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
diff --git a/boards/xtensa/esp32_net/esp32_net_defconfig b/boards/xtensa/esp32_net/esp32_net_defconfig
index 1e9296c..f7846c5 100644
--- a/boards/xtensa/esp32_net/esp32_net_defconfig
+++ b/boards/xtensa/esp32_net/esp32_net_defconfig
@@ -7,8 +7,6 @@
CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
-
CONFIG_CONSOLE=n
CONFIG_SERIAL=n
CONFIG_UART_CONSOLE=n
diff --git a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig b/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig
index 0e8d4af..39a1f24 100644
--- a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig
+++ b/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig
@@ -6,8 +6,6 @@
CONFIG_SOC_ESP32S2=y
CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
-
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig b/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig
index 9e2fd5b..8567404 100644
--- a/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig
+++ b/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig
@@ -6,8 +6,6 @@
CONFIG_SOC_ESP32S2=y
CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
-
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
diff --git a/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig b/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig
index 20bd5f0..68ef048 100644
--- a/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig
+++ b/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig
@@ -7,8 +7,6 @@
CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
-
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
diff --git a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig b/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig
index fe987cb..766659e 100644
--- a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig
+++ b/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig
@@ -7,8 +7,6 @@
CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
-
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
diff --git a/boards/xtensa/odroid_go/odroid_go_defconfig b/boards/xtensa/odroid_go/odroid_go_defconfig
index 84f21a0..4a88a4a 100644
--- a/boards/xtensa/odroid_go/odroid_go_defconfig
+++ b/boards/xtensa/odroid_go/odroid_go_defconfig
@@ -7,8 +7,6 @@
CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
-
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
diff --git a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig b/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig
index 034074e..20f21d9 100644
--- a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig
+++ b/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig
@@ -7,8 +7,6 @@
CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
-
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c
index 9dd7c18..60499de 100644
--- a/drivers/clock_control/clock_control_esp32.c
+++ b/drivers/clock_control/clock_control_esp32.c
@@ -476,7 +476,7 @@
static const struct esp32_clock_config esp32_clock_config0 = {
.clk_src_sel = ESP32_CLOCK_SOURCE,
- .cpu_freq = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency),
+ .cpu_freq = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency) / 10000000,
.xtal_freq_sel = DT_INST_PROP(0, xtal_freq),
.xtal_div = ESP32_CLOCK_XTAL_DIV
};
@@ -492,6 +492,6 @@
#ifndef CONFIG_SOC_ESP32C3
BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) ==
- MHZ(DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency)),
+ DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency),
"SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq");
#endif
diff --git a/include/zephyr/dt-bindings/clock/esp32_clock.h b/include/zephyr/dt-bindings/clock/esp32_clock.h
index d0ef722..65ca36c 100644
--- a/include/zephyr/dt-bindings/clock/esp32_clock.h
+++ b/include/zephyr/dt-bindings/clock/esp32_clock.h
@@ -15,11 +15,11 @@
#define ESP32_CLK_SRC_APLL 3U
/* Supported CPU Frequencies */
-#define ESP32_CLK_CPU_26M 26U
-#define ESP32_CLK_CPU_40M 40U
-#define ESP32_CLK_CPU_80M 80U
-#define ESP32_CLK_CPU_160M 160U
-#define ESP32_CLK_CPU_240M 240U
+#define ESP32_CLK_CPU_26M 26000000
+#define ESP32_CLK_CPU_40M 40000000
+#define ESP32_CLK_CPU_80M 80000000
+#define ESP32_CLK_CPU_160M 160000000
+#define ESP32_CLK_CPU_240M 240000000
/* Supported XTAL Frequencies */
#define ESP32_CLK_XTAL_24M 0U
diff --git a/include/zephyr/dt-bindings/clock/esp32c3_clock.h b/include/zephyr/dt-bindings/clock/esp32c3_clock.h
index 675076f..4c0b6bf 100644
--- a/include/zephyr/dt-bindings/clock/esp32c3_clock.h
+++ b/include/zephyr/dt-bindings/clock/esp32c3_clock.h
@@ -14,8 +14,8 @@
#define ESP32_CLK_SRC_APLL 3U
/* Supported CPU Frequencies */
-#define ESP32_CLK_CPU_80M 80U
-#define ESP32_CLK_CPU_160M 160U
+#define ESP32_CLK_CPU_80M 80000000
+#define ESP32_CLK_CPU_160M 160000000
/* Supported XTAL Frequencies */
#define ESP32_CLK_XTAL_32M 0U
diff --git a/include/zephyr/dt-bindings/clock/esp32s2_clock.h b/include/zephyr/dt-bindings/clock/esp32s2_clock.h
index eee01ce..c61c8b8 100644
--- a/include/zephyr/dt-bindings/clock/esp32s2_clock.h
+++ b/include/zephyr/dt-bindings/clock/esp32s2_clock.h
@@ -14,11 +14,11 @@
#define ESP32_CLK_SRC_APLL 3U
/* Supported CPU Frequencies */
-#define ESP32_CLK_CPU_26M 26U
-#define ESP32_CLK_CPU_40M 40U
-#define ESP32_CLK_CPU_80M 80U
-#define ESP32_CLK_CPU_160M 160U
-#define ESP32_CLK_CPU_240M 240U
+#define ESP32_CLK_CPU_26M 26000000
+#define ESP32_CLK_CPU_40M 40000000
+#define ESP32_CLK_CPU_80M 80000000
+#define ESP32_CLK_CPU_160M 160000000
+#define ESP32_CLK_CPU_240M 240000000
/* Supported XTAL Frequencies */
#define ESP32_CLK_XTAL_40M 0U
diff --git a/soc/xtensa/esp32/Kconfig.defconfig b/soc/xtensa/esp32/Kconfig.defconfig
index 00a26ab..c6af5cb 100644
--- a/soc/xtensa/esp32/Kconfig.defconfig
+++ b/soc/xtensa/esp32/Kconfig.defconfig
@@ -45,6 +45,9 @@
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+ default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
config XTENSA_CCOUNT_HZ
default SYS_CLOCK_HW_CYCLES_PER_SEC
diff --git a/soc/xtensa/esp32_net/Kconfig.defconfig b/soc/xtensa/esp32_net/Kconfig.defconfig
index f484e0a..7484769 100644
--- a/soc/xtensa/esp32_net/Kconfig.defconfig
+++ b/soc/xtensa/esp32_net/Kconfig.defconfig
@@ -13,6 +13,9 @@
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+ default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
config XTENSA_CCOUNT_HZ
default SYS_CLOCK_HW_CYCLES_PER_SEC
diff --git a/soc/xtensa/esp32s2/Kconfig.defconfig b/soc/xtensa/esp32s2/Kconfig.defconfig
index d426638..24e829d 100644
--- a/soc/xtensa/esp32s2/Kconfig.defconfig
+++ b/soc/xtensa/esp32s2/Kconfig.defconfig
@@ -46,6 +46,9 @@
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+ default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
config XTENSA_CCOUNT_HZ
default SYS_CLOCK_HW_CYCLES_PER_SEC
