| commit | 43f0726985e77ae63aafffc3f40da3a2eadef027 | [log] [tgz] |
|---|---|---|
| author | Daniel Leung <daniel.leung@intel.com> | Tue Apr 27 10:19:42 2021 -0700 |
| committer | Anas Nashif <anas.nashif@intel.com> | Thu Apr 29 16:49:17 2021 -0400 |
| tree | 65fe00cc1a7acab48093c8699f9d4c5ac1dab394 | |
| parent | d6cbdace78517045538f2f471989c362fc1b8879 [diff] |
arm: aarch32: timing: fix potential divide by zero if DWT There is a possibility that the DWT frequency calculation is divided by zero. So this fixes the issue by repeatedly trying to get the delta clock cycles and delta DWT cycles until they both are not zero. Signed-off-by: Daniel Leung <daniel.leung@intel.com>