| commit | a6a9a35d0ab1f68fe4b660c7a6948f5c261d01cc | [log] [tgz] |
|---|---|---|
| author | Ederson de Souza <ederson.desouza@intel.com> | Fri Jul 01 13:51:34 2022 -0700 |
| committer | Carles Cufí <carles.cufi@nordicsemi.no> | Sat Jul 02 14:16:39 2022 +0200 |
| tree | a2efe454eea89842bfb0e857ff9f064d31a5457b | |
| parent | f12d36a51e0f44a91b26a4356988656c6b7d39fb [diff] |
doc/hardware/arch: Add RISC-V information This is just a stub with bits of information about RISC-V support on Zephyr, that can and should be improved over time. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>