| commit | 4778c13bbeabbb0ee50f94b28db8a5868e6822ac | [log] [tgz] |
|---|---|---|
| author | Daniel Leung <daniel.leung@intel.com> | Mon Aug 21 15:56:55 2023 -0700 |
| committer | Anas Nashif <anas.nashif@intel.com> | Sat Aug 26 16:50:40 2023 -0400 |
| tree | 6c2c97ac9b8645c808ac11b65c9b30b329c231b4 | |
| parent | c723d8b8d3ac5e0c103c66f82e0b320435d24929 [diff] |
xtensa: mmu: handle all data TLB misses in double exception Instead of only handling data TLB misses for VECBASE, change it to handle all data TLB misses in the double exception handler. It is because we may encounter data TLB misses when trying to preload page table entries inside user exception handler. Signed-off-by: Daniel Leung <daniel.leung@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>