soc: esp32: MCUboot support
This make MCUboot build as Zephyr application.
Providing optinal 2nd stage bootloader to the
IDF bootloader, which is used by default.
This provides more flexibility when building
and loading multiple images and aims to
brings better DX to users by using the sysbuild.
MCUboot and applications has now separate
linker scripts.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
diff --git a/soc/xtensa/esp32s3/loader.c b/soc/xtensa/esp32s3/loader.c
index cf3fafc..d653076 100644
--- a/soc/xtensa/esp32s3/loader.c
+++ b/soc/xtensa/esp32s3/loader.c
@@ -8,12 +8,20 @@
#include <soc.h>
#include <zephyr/storage/flash_map.h>
#include <esp_log.h>
+#include <stdlib.h>
#include <esp32s3/rom/cache.h>
+#include "esp32s3/dport_access.h"
+#include "soc/cache_memory.h"
#include <soc/dport_reg.h>
+#include "soc/extmem_reg.h"
#include <bootloader_flash_priv.h>
#ifdef CONFIG_BOOTLOADER_MCUBOOT
+
+#define BOOT_LOG_INF(_fmt, ...) \
+ ets_printf("[" CONFIG_SOC "] [INF] " _fmt "\n\r", ##__VA_ARGS__)
+
#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
@@ -27,60 +35,54 @@
{
int rc = 0;
size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition);
- uint32_t _app_irom_start = _partition_offset +
- (uint32_t)&_image_irom_start;
+ uint32_t _app_irom_start = _partition_offset + (uint32_t)&_image_irom_start;
uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr;
- uint32_t _app_drom_start = _partition_offset +
- (uint32_t)&_image_drom_start;
+ uint32_t _app_drom_start = _partition_offset + (uint32_t)&_image_drom_start;
uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr;
- Cache_Read_Disable(0);
- Cache_Flush(0);
+ uint32_t autoload = Cache_Suspend_DCache();
+
+ Cache_Invalidate_DCache_All();
+
/* Clear the MMU entries that are already set up,
* so the new app only has the mappings it creates.
*/
- for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
- DPORT_PRO_FLASH_MMU_TABLE[i] =
- DPORT_FLASH_MMU_TABLE_INVALID_VAL;
+ for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
+ FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
}
- uint32_t drom_vaddr_addr_aligned = _app_drom_vaddr & MMU_FLASH_MASK;
- uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size,
- _app_drom_vaddr);
- rc = cache_flash_mmu_set(0, 0, drom_vaddr_addr_aligned, _app_drom_start
- & MMU_FLASH_MASK, 64, drom_page_count);
- rc |= cache_flash_mmu_set(1, 0, drom_vaddr_addr_aligned, _app_drom_start
- & MMU_FLASH_MASK, 64, drom_page_count);
+ uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, _app_drom_vaddr);
- uint32_t irom_vaddr_addr_aligned = _app_irom_vaddr & MMU_FLASH_MASK;
- uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size,
- _app_irom_vaddr);
- rc |= cache_flash_mmu_set(0, 0, irom_vaddr_addr_aligned, _app_irom_start
- & MMU_FLASH_MASK, 64, irom_page_count);
- rc |= cache_flash_mmu_set(1, 0, irom_vaddr_addr_aligned, _app_irom_start
- & MMU_FLASH_MASK, 64, irom_page_count);
+ rc |= esp_rom_Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH,
+ _app_drom_vaddr & MMU_FLASH_MASK,
+ _app_drom_start & MMU_FLASH_MASK,
+ 64, drom_page_count, 0);
- DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG,
- (DPORT_PRO_CACHE_MASK_IRAM0) |
- (DPORT_PRO_CACHE_MASK_IRAM1 & 0) |
- (DPORT_PRO_CACHE_MASK_IROM0 & 0) |
- DPORT_PRO_CACHE_MASK_DROM0 |
- DPORT_PRO_CACHE_MASK_DRAM1);
+ uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, _app_irom_vaddr);
- DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG,
- (DPORT_APP_CACHE_MASK_IRAM0) |
- (DPORT_APP_CACHE_MASK_IRAM1 & 0) |
- (DPORT_APP_CACHE_MASK_IROM0 & 0) |
- DPORT_APP_CACHE_MASK_DROM0 |
- DPORT_APP_CACHE_MASK_DRAM1);
+ rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH,
+ _app_irom_vaddr & MMU_FLASH_MASK,
+ _app_irom_start & MMU_FLASH_MASK,
+ 64, irom_page_count, 0);
- esp_rom_Cache_Read_Enable(0);
+ REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE0_BUS);
+ REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS);
+
+ Cache_Resume_DCache(autoload);
+
+ /* Show map segments continue using same log format as during MCUboot phase */
+ BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map",
+ _app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size);
+ BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n",
+ _app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size);
+ esp_rom_uart_tx_wait_idle(0);
+
return rc;
}
-#endif
+#endif /* CONFIG_BOOTLOADER_MCUBOOT */
void __start(void)
{
