dt-bindings: clock: add stm32l5_clock
This change introduces stm32l5xx clock definitions and separates
it from L4xx series. This change comes because of CCIPR missmatch
of SAI between L4xx and L5xx series.
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
diff --git a/dts/arm/st/l5/stm32l5.dtsi b/dts/arm/st/l5/stm32l5.dtsi
index 9ac9c80..0fcece8 100644
--- a/dts/arm/st/l5/stm32l5.dtsi
+++ b/dts/arm/st/l5/stm32l5.dtsi
@@ -2,12 +2,13 @@
* Copyright (c) 2021 The Chromium OS Authors
* Copyright (c) 2020 Linaro Limited
* Copyright (c) 2024 STMicroelectronics
+ * Copyright (c) 2025 Mario Paja
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv8-m.dtsi>
-#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
+#include <zephyr/dt-bindings/clock/stm32l5_clock.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h
index 9b80fe6..ccce256 100644
--- a/include/zephyr/drivers/clock_control/stm32_clock_control.h
+++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h
@@ -41,9 +41,10 @@
#include <zephyr/dt-bindings/clock/stm32l0_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32L1X)
#include <zephyr/dt-bindings/clock/stm32l1_clock.h>
-#elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
- defined(CONFIG_SOC_SERIES_STM32L5X)
+#elif defined(CONFIG_SOC_SERIES_STM32L4X)
#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
+#elif defined(CONFIG_SOC_SERIES_STM32L5X)
+#include <zephyr/dt-bindings/clock/stm32l5_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
#include <zephyr/dt-bindings/clock/stm32mp2_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32WBX)
diff --git a/include/zephyr/dt-bindings/clock/stm32l4_clock.h b/include/zephyr/dt-bindings/clock/stm32l4_clock.h
index 7fe6e51..cdef7de 100644
--- a/include/zephyr/dt-bindings/clock/stm32l4_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32l4_clock.h
@@ -20,7 +20,7 @@
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
/** Domain clocks */
-/* RM0351/RM0432/RM0438, § Clock configuration register (RCC_CCIPRx) */
+/* RM0351/RM0432, § Clock configuration register (RCC_CCIPRx) */
/** System clock */
/* defined in stm32_common_clocks.h */
diff --git a/include/zephyr/dt-bindings/clock/stm32l5_clock.h b/include/zephyr/dt-bindings/clock/stm32l5_clock.h
new file mode 100644
index 0000000..451f004
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/stm32l5_clock.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2025 Mario Paja
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L5_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L5_CLOCK_H_
+
+#include "stm32_common_clocks.h"
+
+/** Bus clocks */
+#define STM32_CLOCK_BUS_AHB1 0x048
+#define STM32_CLOCK_BUS_AHB2 0x04c
+#define STM32_CLOCK_BUS_AHB3 0x050
+#define STM32_CLOCK_BUS_APB1 0x058
+#define STM32_CLOCK_BUS_APB1_2 0x05c
+#define STM32_CLOCK_BUS_APB2 0x060
+
+#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
+#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
+
+/** Domain clocks */
+/* RM0438, § Clock configuration register (RCC_CCIPRx) */
+
+/** System clock */
+/* defined in stm32_common_clocks.h */
+/** Fixed clocks */
+/* Low speed clocks defined in stm32_common_clocks.h */
+#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
+#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
+#define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
+/** Bus clock */
+#define STM32_SRC_PCLK (STM32_SRC_MSI + 1)
+#define STM32_SRC_TIMPCLK1 (STM32_SRC_PCLK + 1)
+#define STM32_SRC_TIMPCLK2 (STM32_SRC_TIMPCLK1 + 1)
+/** PLL clock outputs */
+#define STM32_SRC_PLL_P (STM32_SRC_TIMPCLK2 + 1)
+#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
+#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
+/* PLLSAI1 clocks */
+#define STM32_SRC_PLLSAI1_P (STM32_SRC_PLL_R + 1)
+#define STM32_SRC_PLLSAI1_Q (STM32_SRC_PLLSAI1_P + 1)
+#define STM32_SRC_PLLSAI1_R (STM32_SRC_PLLSAI1_Q + 1)
+/* PLLSAI2 clocks */
+#define STM32_SRC_PLLSAI2_P (STM32_SRC_PLLSAI1_R + 1)
+#define STM32_SRC_PLLSAI2_Q (STM32_SRC_PLLSAI2_P + 1)
+#define STM32_SRC_PLLSAI2_R (STM32_SRC_PLLSAI2_Q + 1)
+#define STM32_SRC_PLLSAI2_DIVR (STM32_SRC_PLLSAI2_R + 1)
+
+/** @brief RCC_CCIPR register offset */
+#define CCIPR_REG 0x88
+#define CCIPR2_REG 0x9C
+
+/** @brief RCC_BDCR register offset */
+#define BDCR_REG 0x90
+
+/** @brief RCC_CFGRx register offset */
+#define CFGR_REG 0x08
+
+/** @brief Device domain clocks selection helpers */
+/** CCIPR devices */
+#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
+#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
+#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG)
+#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG)
+#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
+#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
+#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
+#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
+#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
+#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
+#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
+#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)
+#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR_REG)
+#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
+#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)
+/** CCIPR2 devices */
+#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
+#define DFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, CCIPR2_REG)
+#define ADFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG)
+#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 5, CCIPR2_REG)
+#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR2_REG)
+#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG)
+#define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG)
+
+/** BDCR devices */
+#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
+/** CFGR devices */
+#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR_REG)
+#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR_REG)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L5_CLOCK_H_ */
