| commit | 4e54cff2232388641a15ad98f56ecad6a6b6582e | [log] [tgz] |
|---|---|---|
| author | Yong Cong Sin <ycsin@meta.com> | Fri Aug 30 12:01:53 2024 +0800 |
| committer | Mahesh Mahadevan <mahesh.mahadevan@nxp.com> | Fri Sep 06 14:06:23 2024 -0500 |
| tree | 8bc3ceb91e1e6a0cf4d6a59303b062fb42c2a663 | |
| parent | a80af336c23f447ad259c492ec8322133a0e3cbf [diff] |
soc: qemu: riscv: update IRQ config - Update `MAX_IRQ_PER_AGGREGATOR` to 1024 to match with the devicetree - Update `2ND_LEVEL_INTERRUPT_BITS` to 11 bits to be able to encode the L2 IRQs. - Update `NUM_IRQS` to 1036 (L1 has 12, L2 has 1024) Update the `MAX_IRQ_PER_AGGREGATOR` config in testcase accordingly, so that it won't overflow the configured bits. Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>