mdio: esp32: fix gpio0 clock output
When GPIO0 is set as RMII clock, configure its
mux to clockout properly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
diff --git a/drivers/ethernet/eth_esp32.c b/drivers/ethernet/eth_esp32.c
index 166064d..eb51cf3 100644
--- a/drivers/ethernet/eth_esp32.c
+++ b/drivers/ethernet/eth_esp32.c
@@ -202,35 +202,6 @@
}
}
-#if DT_INST_NODE_HAS_PROP(0, ref_clk_output_gpios)
-static int emac_config_apll_clock(void)
-{
- uint32_t expt_freq = MHZ(50);
- uint32_t real_freq = 0;
- esp_err_t ret = periph_rtc_apll_freq_set(expt_freq, &real_freq);
-
- if (ret == ESP_ERR_INVALID_ARG) {
- LOG_ERR("Set APLL clock coefficients failed");
- return -EIO;
- }
-
- if (ret == ESP_ERR_INVALID_STATE) {
- LOG_INF("APLL is occupied already, it is working at %d Hz", real_freq);
- }
-
- /* If the difference of real APLL frequency
- * is not within 50 ppm, i.e. 2500 Hz,
- * the APLL is unavailable
- */
- if (abs((int)real_freq - (int)expt_freq) > 2500) {
- LOG_ERR("The APLL is working at an unusable frequency");
- return -EIO;
- }
-
- return 0;
-}
-#endif /* DT_INST_NODE_HAS_PROP(0, ref_clk_output_gpios) */
-
int eth_esp32_initialize(const struct device *dev)
{
struct eth_esp32_dev_data *const dev_data = dev->data;
@@ -281,21 +252,7 @@
if (strcmp(phy_connection_type, "rmii") == 0) {
emac_hal_iomux_init_rmii();
-#if DT_INST_NODE_HAS_PROP(0, ref_clk_output_gpios)
- BUILD_ASSERT(DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 0 ||
- DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 16 ||
- DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 17,
- "Only GPIO0/16/17 are allowed as a GPIO REF_CLK source!");
- int ref_clk_gpio = DT_INST_GPIO_PIN(0, ref_clk_output_gpios);
- emac_hal_iomux_rmii_clk_output(ref_clk_gpio);
- emac_ll_clock_enable_rmii_output(dev_data->hal.ext_regs);
- periph_rtc_apll_acquire();
- res = emac_config_apll_clock();
- if (res != 0) {
- goto err;
- }
- rtc_clk_apll_enable(true);
-#else
+#if !DT_INST_NODE_HAS_PROP(0, ref_clk_output_gpios)
emac_hal_iomux_rmii_clk_input();
emac_ll_clock_enable_rmii_input(dev_data->hal.ext_regs);
#endif
diff --git a/drivers/mdio/mdio_esp32.c b/drivers/mdio/mdio_esp32.c
index 7dd8995..c422c78 100644
--- a/drivers/mdio/mdio_esp32.c
+++ b/drivers/mdio/mdio_esp32.c
@@ -17,6 +17,7 @@
#include <hal/emac_hal.h>
#include <hal/emac_ll.h>
#include <soc/rtc.h>
+#include <soc/io_mux_reg.h>
#include <clk_ctrl_os.h>
LOG_MODULE_REGISTER(mdio_esp32, CONFIG_MDIO_LOG_LEVEL);
@@ -152,15 +153,19 @@
DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 17,
"Only GPIO0/16/17 are allowed as a GPIO REF_CLK source!");
int ref_clk_gpio = DT_INST_GPIO_PIN(0, ref_clk_output_gpios);
-
emac_hal_iomux_rmii_clk_output(ref_clk_gpio);
+
+ /* Configure REF_CLK output when GPIO0 is used */
+ if (ref_clk_gpio == 0) {
+ REG_SET_FIELD(PIN_CTRL, CLK_OUT1, 6);
+ }
+
emac_ll_clock_enable_rmii_output(dev_data->hal.ext_regs);
periph_rtc_apll_acquire();
res = emac_config_apll_clock();
if (res != 0) {
goto err;
}
- rtc_clk_apll_enable(true);
#endif
/* Init MDIO clock */
