driver: dma: update for different dma channels
This patches defines constants from dma registers
depending on the dma configuration of the stm32 soc
Some devices have 6 or 7 or 8 dma channels per dma instance
Signed-off-by: Francois Ramu <francois.ramu@st.com>
diff --git a/drivers/dma/dma_stm32.c b/drivers/dma/dma_stm32.c
index f8c4b85..f558724 100644
--- a/drivers/dma/dma_stm32.c
+++ b/drivers/dma/dma_stm32.c
@@ -605,14 +605,17 @@
IRQ_INIT(0, 4);
#ifdef DT_INST_0_ST_STM32_DMA_IRQ_5
IRQ_INIT(0, 5);
+#ifdef DT_INST_0_ST_STM32_DMA_IRQ_6
IRQ_INIT(0, 6);
#ifdef DT_INST_0_ST_STM32_DMA_IRQ_7
IRQ_INIT(0, 7);
-#endif
-#endif
-/* Either 5 or 7 or 8 channels for DMA1 across all stm32 series. */
+#endif /* DT_INST_0_ST_STM32_DMA_IRQ_5 */
+#endif /* DT_INST_0_ST_STM32_DMA_IRQ_6 */
+#endif /* DT_INST_0_ST_STM32_DMA_IRQ_7 */
+/* Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */
}
-#endif
+#endif /* DT_INST_0_ST_STM32_DMA */
+
#ifdef DT_INST_1_ST_STM32_DMA
DMA_INIT(1);
@@ -621,7 +624,6 @@
{
struct dma_stm32_data *data = dev->driver_data;
-#ifdef DT_INST_1_ST_STM32_DMA_IRQ_0
IRQ_INIT(1, 0);
IRQ_INIT(1, 1);
IRQ_INIT(1, 2);
@@ -629,12 +631,13 @@
IRQ_INIT(1, 4);
#ifdef DT_INST_1_ST_STM32_DMA_IRQ_5
IRQ_INIT(1, 5);
+#ifdef DT_INST_1_ST_STM32_DMA_IRQ_6
IRQ_INIT(1, 6);
#ifdef DT_INST_1_ST_STM32_DMA_IRQ_7
IRQ_INIT(1, 7);
-#endif
-#endif
-#endif
-/* Either 0 or 5 or 7 or 8 channels for DMA1 across all stm32 series. */
+#endif /* DT_INST_1_ST_STM32_DMA_IRQ_5 */
+#endif /* DT_INST_1_ST_STM32_DMA_IRQ_6 */
+#endif /* DT_INST_1_ST_STM32_DMA_IRQ_7 */
+/* Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */
}
-#endif
+#endif /* DT_INST_1_ST_STM32_DMA */
diff --git a/drivers/dma/dma_stm32_v2.c b/drivers/dma/dma_stm32_v2.c
index 760f398..7fbb339 100644
--- a/drivers/dma/dma_stm32_v2.c
+++ b/drivers/dma/dma_stm32_v2.c
@@ -21,8 +21,15 @@
LL_DMA_CHANNEL_3,
LL_DMA_CHANNEL_4,
LL_DMA_CHANNEL_5,
+#if defined(LL_DMA_CHANNEL_6)
LL_DMA_CHANNEL_6,
+#endif /* LL_DMA_CHANNEL_6 */
+#if defined(LL_DMA_CHANNEL_7)
LL_DMA_CHANNEL_7,
+#endif /* LL_DMA_CHANNEL_7 */
+#if defined(LL_DMA_CHANNEL_8)
+ LL_DMA_CHANNEL_8,
+#endif
};
void (*func_ll_clear_ht[])(DMA_TypeDef *DMAx) = {
@@ -31,8 +38,15 @@
LL_DMA_ClearFlag_HT3,
LL_DMA_ClearFlag_HT4,
LL_DMA_ClearFlag_HT5,
+#if defined(LL_DMA_IFCR_CHTIF6)
LL_DMA_ClearFlag_HT6,
+#endif /* LL_DMA_IFCR_CHTIF6 */
+#if defined(LL_DMA_IFCR_CHTIF7)
LL_DMA_ClearFlag_HT7,
+#endif /* LL_DMA_IFCR_CHTIF7 */
+#if defined(LL_DMA_IFCR_CHTIF8)
+ LL_DMA_ClearFlag_HT8,
+#endif /* LL_DMA_IFCR_CHTIF8 */
};
void (*func_ll_clear_tc[])(DMA_TypeDef *DMAx) = {
@@ -41,8 +55,15 @@
LL_DMA_ClearFlag_TC3,
LL_DMA_ClearFlag_TC4,
LL_DMA_ClearFlag_TC5,
+#if defined(LL_DMA_IFCR_CTCIF6)
LL_DMA_ClearFlag_TC6,
+#endif /* LL_DMA_IFCR_CTCIF6 */
+#if defined(LL_DMA_IFCR_CTCIF7)
LL_DMA_ClearFlag_TC7,
+#endif /* LL_DMA_IFCR_CTCIF7 */
+#if defined(LL_DMA_IFCR_CTCIF8)
+ LL_DMA_ClearFlag_TC8,
+#endif /* LL_DMA_IFCR_CTCIF8 */
};
u32_t (*func_ll_is_active_ht[])(DMA_TypeDef *DMAx) = {
@@ -51,8 +72,15 @@
LL_DMA_IsActiveFlag_HT3,
LL_DMA_IsActiveFlag_HT4,
LL_DMA_IsActiveFlag_HT5,
+#if defined(LL_DMA_ISR_HTIF6)
LL_DMA_IsActiveFlag_HT6,
+#endif /* LL_DMA_ISR_HTIF6 */
+#if defined(LL_DMA_ISR_HTIF7)
LL_DMA_IsActiveFlag_HT7,
+#endif /* LL_DMA_ISR_HTIF7 */
+#if defined(LL_DMA_ISR_HTIF8)
+ LL_DMA_IsActiveFlag_HT8,
+#endif /* LL_DMA_ISR_HTIF8 */
};
u32_t (*func_ll_is_active_tc[])(DMA_TypeDef *DMAx) = {
@@ -61,8 +89,15 @@
LL_DMA_IsActiveFlag_TC3,
LL_DMA_IsActiveFlag_TC4,
LL_DMA_IsActiveFlag_TC5,
+#if defined(LL_DMA_ISR_TCIF6)
LL_DMA_IsActiveFlag_TC6,
+#endif /* LL_DMA_ISR_TCIF6 */
+#if defined(LL_DMA_ISR_TCIF7)
LL_DMA_IsActiveFlag_TC7,
+#endif /* LL_DMA_ISR_TCIF7 */
+#if defined(LL_DMA_ISR_TCIF8)
+ LL_DMA_IsActiveFlag_TC8,
+#endif /* LL_DMA_ISR_TCIF8 */
};
static void (*func_ll_clear_te[])(DMA_TypeDef *DMAx) = {
@@ -71,8 +106,15 @@
LL_DMA_ClearFlag_TE3,
LL_DMA_ClearFlag_TE4,
LL_DMA_ClearFlag_TE5,
+#if defined(LL_DMA_IFCR_CTEIF6)
LL_DMA_ClearFlag_TE6,
+#endif /* LL_DMA_IFCR_CTEIF6 */
+#if defined(LL_DMA_IFCR_CTEIF7)
LL_DMA_ClearFlag_TE7,
+#endif /* LL_DMA_IFCR_CTEIF7 */
+#if defined(LL_DMA_IFCR_CTEIF8)
+ LL_DMA_ClearFlag_TE8,
+#endif /* LL_DMA_IFCR_CTEIF8 */
};
static void (*func_ll_clear_gi[])(DMA_TypeDef *DMAx) = {
@@ -81,8 +123,15 @@
LL_DMA_ClearFlag_GI3,
LL_DMA_ClearFlag_GI4,
LL_DMA_ClearFlag_GI5,
+#if defined(LL_DMA_IFCR_CGIF6)
LL_DMA_ClearFlag_GI6,
+#endif /* LL_DMA_IFCR_CGIF6 */
+#if defined(LL_DMA_IFCR_CGIF7)
LL_DMA_ClearFlag_GI7,
+#endif /* LL_DMA_IFCR_CGIF7 */
+#if defined(LL_DMA_IFCR_CGIF8)
+ LL_DMA_ClearFlag_GI8,
+#endif /* LL_DMA_IFCR_CGIF8 */
};
static u32_t (*func_ll_is_active_te[])(DMA_TypeDef *DMAx) = {
@@ -91,8 +140,15 @@
LL_DMA_IsActiveFlag_TE3,
LL_DMA_IsActiveFlag_TE4,
LL_DMA_IsActiveFlag_TE5,
+#if defined(LL_DMA_IFCR_CTEIF6)
LL_DMA_IsActiveFlag_TE6,
+#endif /* LL_DMA_IFCR_CTEIF6 */
+#if defined(LL_DMA_IFCR_CTEIF7)
LL_DMA_IsActiveFlag_TE7,
+#endif /* LL_DMA_IFCR_CTEIF7 */
+#if defined(LL_DMA_IFCR_CTEIF8)
+ LL_DMA_IsActiveFlag_TE8,
+#endif /* LL_DMA_IFCR_CTEIF8 */
};
@@ -102,8 +158,16 @@
LL_DMA_IsActiveFlag_GI3,
LL_DMA_IsActiveFlag_GI4,
LL_DMA_IsActiveFlag_GI5,
+#if defined(LL_DMA_IFCR_CGIF6)
LL_DMA_IsActiveFlag_GI6,
+#endif /* LL_DMA_IFCR_CGIF6 */
+#if defined(LL_DMA_IFCR_CGIF7)
LL_DMA_IsActiveFlag_GI7,
+#endif /* LL_DMA_IFCR_CGIF7 */
+#if defined(LL_DMA_IFCR_CGIF8)
+ LL_DMA_IsActiveFlag_GI8,
+#endif /* LL_DMA_IFCR_CGIF8 */
+
};
void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, u32_t id)
