soc/xtensa/intel_adsp: Upstream updates
Significant rework of the Intel Audio DSP SoC/board layers. Includes
code from the following upstream commits:
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Thu Jun 25 16:34:36 2020 +0100
xtesna: adsp: use 50k ticks per sec for audio
Audio needs high resolution scheduling so schedule to nearest 20uS.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 24 13:59:01 2020 -0700
soc/xtensa/intel_adsp: Remove sof-config.h includes
This header isn't used any more, and in any case shouldn't be included
by SoC-layer Zephyr headers that need to be able to build without SOF.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Sat Jun 20 15:42:58 2020 -0700
soc/intel_adsp: Leave interrupts disabled at MP startup
This had some code that was pasted in from esp32 that was inexplicably
enabling interrupts when starting an auxiliary CPU. The original
intent was that the resulting key would be passed down to the OS, but
that's a legacy SMP mechanism and unused. What it actually did was
SET the resulting value in PS.INTLEVEL, enabling interrupts globally
before the CPU is ready to handle them.
Just remove. The system doesn't need to enable interrupts until the
entrance to the first user thread on this CPU, which will do it
automatically as part of the context switch.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 13:57:54 2020 +0300
dts: intel_cavs: Add required label
Add required label fixing build for CAVS15, 20, 25.
Fixes following errors:
...
devicetree error: 'label' is marked as required in 'properties:' in
bindings/interrupt-controller/intel,cavs-intc.yaml,
but does not appear in
...
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 15:19:56 2020 +0300
soc: cavs_v18: Remove dts_fixup and fix build
Remove unused now dts_fixup.h and fix build with the recent code base.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 15:12:25 2020 +0300
soc: cavs_v20: Remove dts_fixup and fix build
Remove unused now dts_fixup.h and fix build with the recent code base.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 14:59:23 2020 +0300
soc: cavs_v25: Remove dts_fixup fix build
Remove unused now dts_fixup and fix build with the latest code base.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 12 12:29:06 2020 +0300
soc: intel_adsp: Remove unused functions
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 17:53:58 2020 +0300
soc: intel_adsp: Clean up soc.h
Remove unused or duplicated definitions.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 17:02:23 2020 +0300
soc: intel_adsp: De-duplicate soc.h
Move soc.h to common SOC area.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 15:54:19 2020 +0300
soc: intel_adsp: Remove duplicated io.h
Move duplicated io.h to common SOC area.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 12 12:39:46 2020 +0300
cmake: Correct SOC_SERIES name for byt and bdw
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 12 12:39:02 2020 +0300
soc: intel_adsp: Build bootloader only for specific SOCs
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Thu Jun 11 13:46:25 2020 +0100
boards: xtensa: adsp: add byt and bdw boards WIP
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 10 10:01:29 2020 -0700
soc/intel_adsp: Make the HDA timer the default always
The CAVS_TIMER was originally written because the CCOUNT values are
skewed between SMP CPUs, so it's the default when SMP=y. But really
it should be the default always, the 19.2 MHz timer is plenty fast
enough to be the Zephyr cycle timer, and it's rate is synchronized
across the whole system (including the host CPU), making it a better
choice for timing-sensitive applications.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 15:21:43 2020 +0300
soc: cavs_v25: Enable general samples build
Enables general samples build for SOC cavs_v25.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 15:13:53 2020 +0300
soc: cavs_v20: Enable general samples build
Enable general sample build.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 14:35:13 2020 +0300
soc: cavs_v18: Fix build general samples
Fix building general samples for CAVS18.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 14:22:40 2020 +0300
soc: intel_adsp: Add support for other SOCs
Support other SOCs in the "ready" message to the Host.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 13:25:39 2020 +0300
soc: intel_adsp: Move adsp.c to common SOC area
Move adsp.c to common and clean makefiles.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 17:18:18 2020 +0300
boards: intel_adsp: Remove dependency on SOF
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 9 14:29:44 2020 +0100
soc: xtensa: cavs: build now good for cavs20 + 25
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 15:57:01 2020 +0300
soc: cavs_v15: Fix build for hello_world
Fix build for other then audio/sof targets.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 14:50:12 2020 +0300
sample: audio/sof: Remove old overlays
Removing old overlays used to switch logging backend.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon Jun 8 15:02:01 2020 +0300
soc: intel_adsp: Correct TEXT area
Correct HEADER_SPACE and put TEXT to:
(HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE + VECTOR_TBL_SIZE)
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 14:44:47 2020 +0300
soc: intel_adsp: Trivial syntax cleanup
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 14:41:07 2020 +0300
soc: intel_adsp: Fix bootloader script path
Make it possible to find linker script if build is done not inside
ZEPHYR_BASE.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 9 12:10:17 2020 +0100
soc: xtensa: cavs20/25: fix build with new headers - WIP
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 13:35:38 2020 +0300
soc: intel_adsp: Fix include headers
Fixes include headers
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 9 10:38:50 2020 +0100
soc: xtensa: cav18: updated headers- WIP
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Fri May 1 15:29:26 2020 -0700
soc/xtensa/intel_adsp: Clean up MP config logic
CONFIG_MP_NUM_CPUS is a platform value, indicating the number of CPUs
for which the Zephyr image is built. This is the value kernel and
device code should use to predicate questions like "is there more than
one CPU?"
CONFIG_SMP is an application tunable, controlling whether or not the
kernel schedules threads on CPUs other than the first one. This is
orthogonal to MP_NUM_CPUS: it's possible to build a "SMP" kernel on a
uniprocessor system or have a UP kernel on a MP system if the other
cores are used for non-thread application code.
CONFIG_SCHED_IPI_SUPPORTED is a platform flag telling an SMP kernel
whether or not it can synchronously signal other CPUs of scheduler
state changes. It should be inspected only inside the scheduler (or
other code that uses the API). This should be selected in kconfig by
soc layer code, or by a driver that implements the feature.
CONFIG_IPM_CAVS_IDC is a driver required to implement IPI on this
platform. This is what we should use as a predicate if we have
dependence on the IPM driver for a platform feature.
These were all being sort of borged together in code. Split them up
correctly, allowing the platform MP layer to be unit tested in the
absence of SMP (c.f. tests/kernel/mp), and SMP kernels with only one
CPU (which is pathlogical in practice, but also a very good unit test)
to be built.
Also removes some dead linker code for SMP-related sections that don't
exist in Zephyr.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Jun 8 16:41:55 2020 +0100
soc: xtensa: bootloader - use linker script
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Jun 8 16:26:18 2020 +0100
soc: xtensa: further fix headers - WIP
Simplify the directory structure, WIP for cavs20 and cavs25
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon Jun 8 12:59:30 2020 +0300
soc: cavs_v15: Remove unneeded include
Remove include fixing build.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun Jun 7 12:37:35 2020 +0100
soc:xtensa: adsp: remove sof specific code from soc headers
TODO: v1.8+
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Marc Herbert <marc.herbert@intel.com>
Date: Thu Jun 4 23:19:37 2020 -0700
intel_adsp_*/doc: fix duplicate .rst labels
Quick fix purely to make the build green again.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Author: Marc Herbert <marc.herbert@intel.com>
Date: Thu Jun 4 22:34:40 2020 -0700
samples/audio/sof: use OVERLAY_CONFIG to import apollolake_defconfig
This reverts commit 21f16b5b1d29fca83d1b62b1b75683b5a1bc2935 that
copied it here instead.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 5 12:34:48 2020 +0300
soc: intel_adsp: Move soc_mp to common
Moving soc_mp to common SOC area, it still needs fixes for taking
number of cores from Zephyr Kconfig, etc.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 16:05:06 2020 +0300
soc: intel_adsp: Move memory.h from lib/
For those files from SOF referencing platform/lib/memory.h we have
include.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 15:20:09 2020 +0300
soc: intel_adsp: Rename platform.h to soc.h
Rename to prevent including it from SOF.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 11:47:55 2020 +0300
soc: intel_adsp: Move headers
Move headers to more convenient place
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 11:21:51 2020 +0300
soc: intel_adsp: More SOC cleaning
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Marc Herbert <marc.herbert@intel.com>
Date: Mon Jun 1 15:31:34 2020 -0700
samples/audio/sof: import sof/src/arch/xtensa/ apollolake_defconfig
Import modules/audio/sof/src/arch/xtensa/configs/apollolake_defconfig
into prj.conf and new boards/up_squared_adsp.conf
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 15:07:40 2020 +0100
soc:xtensa: adsp: let SOF configure the DSP for audio
Let SOF do this for the moment.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 15:06:20 2020 +0100
soc: xtensa: cavs: remove headers similar to cavs15
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 3 15:58:38 2020 +0300
soc: intel_adsp: Move ipc header to common
Remove duplicated headers from CAVS to common SOC part
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 3 13:02:09 2020 +0300
soc: cavs_v15: Remove unneeded headers
Remove also from CAVS15.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 18:34:11 2020 +0300
Remove more headers
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 14:12:09 2020 +0100
soc: xtensa: remove cavs sod headers for drivers and trace.
Duplicate cavs15 headers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 14:05:12 2020 +0100
samples: move sof dai, dma and clk configs to SOF
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 17:38:45 2020 +0300
soc: intel_adsp: Remove more duplicated headers
Remove more headers
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 2 15:50:03 2020 +0100
samples: sof: remove pm realted files.
Use the SOF versions.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 16:55:40 2020 +0300
WIP: Strip lib from include path
WIP, pushed for sync
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 14:44:33 2020 +0300
soc: intel_adsp: Remove more headers
Remove even more common headers
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 14:00:47 2020 +0300
soc: intel_adsp: Remove SOF headers
The headers would be used by audio/sof app directly from SOF module.
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Sat May 30 11:01:26 2020 -0700
soc/intel_adsp: Alternative log reading script
This script speaks the same protocol and works with the same firmware,
but:
* Is a single file with no dependencies outside the python3 standard
library and can be run out-of-tree (i.e. with setups where the
firmware is not built on the device under test)
* Operates in "tail" mode, where it will continue polling for more
output, making it easier to watch a running process and acting more
like a conventional console device.
* Has no dependence on the diag_driver kernel module (it reads the DSP
SRAM memory directly from the BAR mapping in the PCI device)
* Is MUCH smaller than the existing tool.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu May 28 16:17:51 2020 +0300
Decrease HEP pool size to 192000
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:27:00 2020 +0100
soc: xtensa: cavs25: complete support for cavs25
Builds, not tested on qmeu due to missing SOF ROM (TODO)
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:24:26 2020 +0100
soc: xtensa: cavs20: complete cavs20 support
Now boots on qemu.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:22:13 2020 +0100
soc: xtensa: cavs18: complete boot support
Now boots on qemu.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:19:23 2020 +0100
soc: xtensa: cavs15: use cavs15 instead of apl as linker soc name
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:16:06 2020 +0100
TODO: samples: sof: work around missing trace symbols.
Disable local trace.
Needs trace updates finished before this can be removed.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:57:19 2020 +0100
dts: xtensa: rename apl to cavs15 DTS
This DTS is used by more than APL SOC. i.e. all CAVS15 SOCs
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:52:20 2020 +0100
west: commands: sign: Add signing support for other CAVS targets
Sign for CAVS15, CAVS18, CAVS20 and CAVS25 SOCs
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:50:07 2020 +0100
boards: xtensa: cavs: used Zephyr mask macro
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:49:46 2020 +0100
soc: xtensa: move code to SOF
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue May 26 11:40:36 2020 +0100
soc: xtensa: use SOF versions of clk
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 18:38:45 2020 +0300
soc: intel_adsp: Send FW ready for non SOF configuration
Configure windows and send FW ready when used without SOF, should be
loaded with fw_loader script.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 18:02:22 2020 +0300
soc: intel_adsp: Use SOF version of the file
Use exact copy from SOF module.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:47:27 2020 +0300
soc: intel_adsp: Clean up include headers
Remove SOF mentions from the SOC headers.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:43:05 2020 +0300
soc: intel_adsp: Move SOF specific code to samples/audio/sof
Move SOF specific code to the SOF sample.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:39:42 2020 +0300
soc: intel_adsp: Use SOF module's version of mem_window.c
Use exact copy from SOF module.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:36:41 2020 +0300
soc: intel_adsp: Use exact copy from SOF module
Use SOF module verion of the clk.c
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 14:03:35 2020 +0300
soc: xtensa: Add {SOC_FAMILY}/common/include path
Add ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include path if exist.
Fixes issues for xtensa SOCs.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 25 16:18:50 2020 +0100
soc: xtensa: cavs common: fix headers for build
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 25 16:10:57 2020 +0100
soc: xtensa: adsp: add so_inthandlers.h for Intel platforms
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 25 16:08:26 2020 +0100
cmake: xtensa: select correct compiler per CAVS target.
TODO: what about XCC ?
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue May 19 14:59:26 2020 +0300
boards: up_squared_adsp: Move SOF configuration to samples
Move SOF-specific configuration to samples/audio/sof prj.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri May 15 15:29:50 2020 +0300
soc: intel_adsp: Move SOF code to modules/audio/sof
Move SOF dependent code out of SOC area.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu May 14 17:30:38 2020 +0300
Move task_main_start() to audio/sof sample
Start task_main_start() from main of audio/sof sample.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed May 13 15:37:20 2020 +0300
Rename up_xtreme_adsp to intel_adsp_cavs18
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon Apr 27 14:12:59 2020 +0300
Add sample audio/sof for SOF initialization
Add dedicated sample where we put SOF specific initialization.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 11 18:49:36 2020 +0300
WIP: soc: cavs_v18: Cleanup
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 11 15:44:06 2020 +0300
soc: cavs_v15: Move soc init to common part
Moving SOC init to the right place.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 11 15:02:28 2020 +0300
soc: intel_adsp: Move common part to special dir
Moving common part to common/adsp.c
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri May 8 14:37:50 2020 +0300
boards: up_xtreme_adsp: Add initial up_xtreme_adsp board
Add initial board copying existing up_squared_adsp board and using
CAVS1.8 SOC family.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu May 7 15:30:51 2020 +0300
soc: intel_adsp: Generalize bootloader
Move bootloader to soc/xtensa/intel_adsp making it available for other
boards.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue May 5 21:31:00 2020 +0100
boards: xtensa: up_squared: Add support for all CAVS
Add boot support for all CAVS versions. TODO: needs to be made common
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue May 5 21:25:34 2020 +0100
soc: xtensa: intel_adsp: Manage cache for DMA descriptors
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 4 21:10:50 2020 +0100
soc: xtensa: adsp: use 24M567 clock
Use audio clock
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 4 10:04:01 2020 +0100
xtensa: soc: adsp: enable system agent
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 15:03:07 2020 +0100
soc: xtensa: intel_adsp: increase mem pool to 192k
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 15:02:31 2020 +0100
soc: xtensa: intel_adsp: re-enable DMA trace
Buffer will be empty (as trace items sent to Zephyr LOG) but
logic is running.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 11:18:55 2020 +0100
soc: xtensa: intel: dont use uncache region yet.
Some code was still using this region. Use later.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 10:07:28 2020 +0100
soc: xtensa: intel_adsp: fix notifier init
Topology now loads.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 1 21:18:38 2020 +0100
boards: up2: Need to use sof config for bootloader
This will need uncoupled at some point. For testing today.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 1 21:16:38 2020 +0100
boards: up2: increase heap to 128k
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Apr 30 11:35:19 2020 +0300
boards: up_squared_adsp: Use bigger HEAP
Use HEAP from old demo.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 1 16:06:32 2020 +0100
soc: xtensa: intel_adsp: Fix config.h naming collisions
Rename sof version to sof-config.h
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Apr 30 11:22:42 2020 +0300
Small cleanups
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 29 22:00:44 2020 +0300
tests: sof/audio: Test ll scheduler
Add more tests for scheduler.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 29 18:38:35 2020 +0300
tests: Add first schedule test
Add initial test for testing scheduling.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 29 13:36:23 2020 +0100
soc: xtensa: rmeove build warnings
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 28 18:04:33 2020 +0300
soc/intel_adsp: Register sof logging
Register sof logging for tracing
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 28 14:16:55 2020 +0300
boards: up_squared_adsp: Define HEAP_MEM_POOL_SIZE
Define HEAP_MEM_POOL_SIZE when SOF enabled.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 28 10:09:20 2020 +0300
tests: audio/sof: Add interrupt API for testing
Add initial interrupt API for testing.
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 27 15:54:28 2020 +0100
soc: xtensa: adsp: Update linker script for SOF sections.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 27 11:20:01 2020 +0100
soc: xtensa: adsp: send SOF FW metadata as boot message
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun Apr 26 21:47:20 2020 +0100
soc: xtensa: adsp: re-enable all SOF IP init.
Do all SOF IP init.
TODO: ATOMCTL, WFI on LX6
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sat Apr 25 15:30:40 2020 +0100
soc: xtensa: irq: Make sure IPC IRQ is registered.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 22 20:56:09 2020 +0300
tests: sof: Enable console
Enable console for the test.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 22 17:57:22 2020 +0300
soc: cavs_v15: Fix XTENSA_KERNEL_CPU_PTR_SR
Use correct value for XTENSA_KERNEL_CPU_PTR_SR.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 22 14:48:31 2020 +0300
tests: audio/sof: Add tests for alloc API testing
Add initial tests for allocation API testing. Can be extended for
other later.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 21 17:49:32 2020 +0300
logging: Enable xtensa simulator backend for ADSP
Enable xtensa simulator backend for SOC_FAMILY_INTEL_ADSP.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 20:58:30 2020 +0100
soc: xtensa: add common cpu logic
Support for additional cores.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 21 10:11:07 2020 +0300
Update west.yaml to point to the latest repo
Update west.yaml
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:17:01 2020 +0100
soc: xtensa: cavs: Fix build for clk.c on cavs18+
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:05:31 2020 +0100
soc: xtensa: cavs15: removed unused headers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:05:09 2020 +0100
soc: xtensa: cavs25: align with SOF headers
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:03:52 2020 +0100
soc: xtensa: cavs20: align with SOF headers
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:03:09 2020 +0100
soc: xtensa: cavs18: Align with SOF headers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 11:42:39 2020 +0100
west: sof: Updated to latest version.
Now builds, links and runs SOF code (but not to FW ready).
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun Apr 19 13:28:53 2020 +0100
xtensa: intel adsp: build in SOF symbols if CONFIG_SOF
Code now fully links against SOF. Needs to be run tested.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Wed Apr 15 10:19:28 2020 -0700
DO NOT MERGE: temporarily add thesoftproject as remote for sof module
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Wed Apr 15 10:33:40 2020 -0700
ipm: cavs_idc: use the IPC/IDC definitions in SoC
The SoC definitions have the necessary IPC/IDC bits so there is
no need to define them separately.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 14:30:20 2020 +0100
TODO: config: Use static config for SOF module.
TODO: needs to be generated as part of SOF kconfig
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri Apr 10 21:56:07 2020 +0100
HACK: Add SOF into build
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 13:55:15 2020 +0100
west: modules: Add SOF audio module.
Add support for building SOF as a Zephyr module. This is the starting
point for add SOF audio into Zephyr. Currently builds but does not use
any symbols yet.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 13:48:48 2020 +0100
WIP soc: adsp-cavs15: Use same include directory structure as SOF
Use the same directory structure as SOF to simplify porting and allow
SOF to build without Zephyr until porting work is complete.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 13:43:44 2020 +0100
WIP soc: adsp-common: Use same include directory structure as SOF
Use the same directory structure as SOF to simplify porting and allow
SOF to build without Zephyr until porting work is complete.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 14:36:32 2020 +0000
WIP: soc: adsp-common: cache is common across all Intel ADSP platforms
De-duplicate soc.h cache definitions.
TODO: this needs done for other common functions.
TODO: need to fix include path
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 30 11:07:43 2020 -0700
WIP: soc: cavs25: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 30 11:07:12 2020 -0700
WIP: soc: cavs20: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 30 11:06:40 2020 -0700
WIP: soc: cavs18: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 12:37:17 2020 -0700
soc: intel_adsp: use main_entry.S in common for cavs_v15
The files are identical anyway.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 11:38:14 2020 -0700
soc: intel_adsp/cavs_v15: link common code
Let cavs_v15 link against the code compiled under common/.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 13:08:28 2020 +0000
WIP: soc: common: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 14:37:32 2020 +0000
WIP soc: adsp-cavs15: build power down support
Build the power down support for CAVS1.5
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 12:40:17 2020 +0000
WIP: soc: cavs15: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 14:30:08 2020 +0000
soc: cavs15: Add missing SHIM registers.
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 9 15:43:01 2020 +0000
xtensa: intel_adsp/cavs_v15: fix usage of LP SRAM power gating
Remove LSPGCTL as it can cause confusion, use SHIM_LSPGCTL instead.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Feb 26 15:28:48 2020 +0000
boards: up_squared_adsp: Use local xtensa HAL instead of SDK HAL
SDK HAL is deprecated for Intel ADSP SoCs so fix and use local HAL
module.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 10:45:15 2020 -0700
soc: add Intel Audio DSP SoC family
This creates a SoC family for the audio DSPs on various
Intel CPUs. The intel_apl_adsp is being moved into
this family as well, since it is part of the CAVS v1.5
series of DSPs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 11:29:02 2020 -0700
soc: xtensa: add CMakeLists.txt
Add CMakeLists.txt under soc/xtensa so that CMakeLists.txt
inside each SoC directory will be included, similar to
what ARM and RISCV have.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 17 12:30:43 2020 -0700
Revert "boards: up_squared_adsp: Add flasher script"
This reverts commit 80f295a9dd259f75f201c09abee849f1780efaff.
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 17 12:30:32 2020 -0700
Revert "boards: up_squared_adsp: Update logtool tool"
This reverts commit 7770d182c15b8173cade5804a0889b69291354d4.
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 17 12:30:23 2020 -0700
Revert "soc: intel_adsp: Generalize bootloader"
This reverts commit d6a33ef4677dddd7c76d4672ebec82352448c1d2.
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
soc: xtensa; intel: remove sof-config.h - SQUASH
No longer used.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 6dcb8bf..f267696 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -84,6 +84,7 @@
${SOC_DIR}/${ARCH}/${SOC_PATH}
${SOC_DIR}/${ARCH}/${SOC_PATH}/include
${SOC_DIR}/${ARCH}/${SOC_FAMILY}/include
+ ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include
)
if(EXISTS ${optional_include_dir})
zephyr_include_directories(${optional_include_dir})
diff --git a/boards/xtensa/intel_adsp_cavs18/Kconfig.board b/boards/xtensa/intel_adsp_cavs18/Kconfig.board
new file mode 100644
index 0000000..765bfe0
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs18/Kconfig.board
@@ -0,0 +1,8 @@
+# Xtensa board configuration
+
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INTEL_ADSP_CAVS18
+ bool "Intel ADSP CAVS 1.8"
+ depends on SOC_SERIES_INTEL_CAVS_V18
diff --git a/boards/xtensa/intel_adsp_cavs18/Kconfig.defconfig b/boards/xtensa/intel_adsp_cavs18/Kconfig.defconfig
new file mode 100644
index 0000000..3bd5423
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs18/Kconfig.defconfig
@@ -0,0 +1,46 @@
+# Copyright (c) 2020 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_INTEL_ADSP_CAVS18
+
+config BOARD
+ default "intel_adsp_cavs18"
+
+config CAVS_ICTL_0_OFFSET
+ default 6
+config CAVS_ICTL_1_OFFSET
+ default 10
+config CAVS_ICTL_2_OFFSET
+ default 13
+config CAVS_ICTL_3_OFFSET
+ default 16
+
+config 2ND_LVL_INTR_00_OFFSET
+ default CAVS_ICTL_0_OFFSET
+config 2ND_LVL_INTR_01_OFFSET
+ default CAVS_ICTL_1_OFFSET
+config 2ND_LVL_INTR_02_OFFSET
+ default CAVS_ICTL_2_OFFSET
+config 2ND_LVL_INTR_03_OFFSET
+ default CAVS_ICTL_3_OFFSET
+
+config MAX_IRQ_PER_AGGREGATOR
+ default 32
+config NUM_2ND_LEVEL_AGGREGATORS
+ default 4
+config 2ND_LVL_ISR_TBL_OFFSET
+ default 21
+
+config CAVS_ISR_TBL_OFFSET
+ default 2ND_LVL_ISR_TBL_OFFSET
+
+config DMA_DW
+ default y
+ depends on DMA
+
+config I2S_CAVS
+ default y
+ depends on I2S
+
+endif # BOARD_INTEL_ADSP_CAVS18
diff --git a/boards/xtensa/intel_adsp_cavs18/board.cmake b/boards/xtensa/intel_adsp_cavs18/board.cmake
new file mode 100644
index 0000000..6b01bab
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs18/board.cmake
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(misc-flasher)
+board_finalize_runner_args(misc-flasher)
diff --git a/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18.dts b/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18.dts
new file mode 100644
index 0000000..a0f9726
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <intel/intel_cavs18.dtsi>
+
+/ {
+ model = "intel_adsp_cavs18";
+ compatible = "intel";
+
+ chosen {
+ zephyr,sram = &sram0;
+ };
+};
diff --git a/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18.yaml b/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18.yaml
new file mode 100644
index 0000000..611515d
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18.yaml
@@ -0,0 +1,9 @@
+identifier: intel_adsp_cavs18
+name: CAVS 1.8 Audio DSP (Connected Audio Voice and Speech)
+type: mcu
+arch: xtensa
+toolchain:
+ - zephyr
+testing:
+ only_tags:
+ - kernel
diff --git a/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18_defconfig b/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18_defconfig
new file mode 100644
index 0000000..943e716
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18_defconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+
+CONFIG_SOC_SERIES_INTEL_CAVS_V18=y
+CONFIG_BOARD_INTEL_ADSP_CAVS18=y
+
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+
+CONFIG_XTENSA_RESET_VECTOR=y
+
+CONFIG_XTENSA_USE_CORE_CRT1=y
+
+CONFIG_MULTI_LEVEL_INTERRUPTS=y
+CONFIG_2ND_LEVEL_INTERRUPTS=y
+CONFIG_CAVS_ICTL=y
+
+CONFIG_BOOTLOADER_SRAM_SIZE=192
diff --git a/boards/xtensa/intel_adsp_cavs20/Kconfig.board b/boards/xtensa/intel_adsp_cavs20/Kconfig.board
new file mode 100644
index 0000000..64e8990
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs20/Kconfig.board
@@ -0,0 +1,8 @@
+# Xtensa board configuration
+
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INTEL_ADSP_CAVS20
+ bool "Intel ADSP CAVS 2.0"
+ depends on SOC_SERIES_INTEL_CAVS_V20
diff --git a/boards/xtensa/intel_adsp_cavs20/Kconfig.defconfig b/boards/xtensa/intel_adsp_cavs20/Kconfig.defconfig
new file mode 100644
index 0000000..b7815d9
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs20/Kconfig.defconfig
@@ -0,0 +1,46 @@
+# Copyright (c) 2020 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_INTEL_ADSP_CAVS20
+
+config BOARD
+ default "intel_adsp_cavs20"
+
+config CAVS_ICTL_0_OFFSET
+ default 6
+config CAVS_ICTL_1_OFFSET
+ default 10
+config CAVS_ICTL_2_OFFSET
+ default 13
+config CAVS_ICTL_3_OFFSET
+ default 16
+
+config 2ND_LVL_INTR_00_OFFSET
+ default CAVS_ICTL_0_OFFSET
+config 2ND_LVL_INTR_01_OFFSET
+ default CAVS_ICTL_1_OFFSET
+config 2ND_LVL_INTR_02_OFFSET
+ default CAVS_ICTL_2_OFFSET
+config 2ND_LVL_INTR_03_OFFSET
+ default CAVS_ICTL_3_OFFSET
+
+config MAX_IRQ_PER_AGGREGATOR
+ default 32
+config NUM_2ND_LEVEL_AGGREGATORS
+ default 4
+config 2ND_LVL_ISR_TBL_OFFSET
+ default 21
+
+config CAVS_ISR_TBL_OFFSET
+ default 2ND_LVL_ISR_TBL_OFFSET
+
+config DMA_DW
+ default y
+ depends on DMA
+
+config I2S_CAVS
+ default y
+ depends on I2S
+
+endif # BOARD_INTEL_ADSP_CAVS20
diff --git a/boards/xtensa/intel_adsp_cavs20/board.cmake b/boards/xtensa/intel_adsp_cavs20/board.cmake
new file mode 100644
index 0000000..6b01bab
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs20/board.cmake
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(misc-flasher)
+board_finalize_runner_args(misc-flasher)
diff --git a/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20.dts b/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20.dts
new file mode 100644
index 0000000..2381c11
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <intel/intel_cavs20.dtsi>
+
+/ {
+ model = "intel_adsp_cavs20";
+ compatible = "intel";
+
+ chosen {
+ zephyr,sram = &sram0;
+ };
+};
diff --git a/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20.yaml b/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20.yaml
new file mode 100644
index 0000000..b5a015f
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20.yaml
@@ -0,0 +1,9 @@
+identifier: intel_adsp_cavs20
+name: CAVS 2.0 Audio DSP (Connected Audio Voice and Speech)
+type: mcu
+arch: xtensa
+toolchain:
+ - zephyr
+testing:
+ only_tags:
+ - kernel
diff --git a/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_defconfig b/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_defconfig
new file mode 100644
index 0000000..e677f66
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_defconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+
+CONFIG_SOC_SERIES_INTEL_CAVS_V20=y
+CONFIG_BOARD_INTEL_ADSP_CAVS20=y
+
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+
+CONFIG_XTENSA_RESET_VECTOR=y
+
+CONFIG_XTENSA_USE_CORE_CRT1=y
+
+CONFIG_MULTI_LEVEL_INTERRUPTS=y
+CONFIG_2ND_LEVEL_INTERRUPTS=y
+CONFIG_CAVS_ICTL=y
+
+CONFIG_BOOTLOADER_SRAM_SIZE=192
diff --git a/boards/xtensa/intel_adsp_cavs25/Kconfig.board b/boards/xtensa/intel_adsp_cavs25/Kconfig.board
new file mode 100644
index 0000000..8b20c41
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs25/Kconfig.board
@@ -0,0 +1,8 @@
+# Xtensa board configuration
+
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INTEL_ADSP_CAVS25
+ bool "Intel ADSP CAVS 2.5"
+ depends on SOC_SERIES_INTEL_CAVS_V25
diff --git a/boards/xtensa/intel_adsp_cavs25/Kconfig.defconfig b/boards/xtensa/intel_adsp_cavs25/Kconfig.defconfig
new file mode 100644
index 0000000..d21aa27
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs25/Kconfig.defconfig
@@ -0,0 +1,46 @@
+# Copyright (c) 2020 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_INTEL_ADSP_CAVS25
+
+config BOARD
+ default "intel_adsp_cavs25"
+
+config CAVS_ICTL_0_OFFSET
+ default 6
+config CAVS_ICTL_1_OFFSET
+ default 10
+config CAVS_ICTL_2_OFFSET
+ default 13
+config CAVS_ICTL_3_OFFSET
+ default 16
+
+config 2ND_LVL_INTR_00_OFFSET
+ default CAVS_ICTL_0_OFFSET
+config 2ND_LVL_INTR_01_OFFSET
+ default CAVS_ICTL_1_OFFSET
+config 2ND_LVL_INTR_02_OFFSET
+ default CAVS_ICTL_2_OFFSET
+config 2ND_LVL_INTR_03_OFFSET
+ default CAVS_ICTL_3_OFFSET
+
+config MAX_IRQ_PER_AGGREGATOR
+ default 32
+config NUM_2ND_LEVEL_AGGREGATORS
+ default 4
+config 2ND_LVL_ISR_TBL_OFFSET
+ default 21
+
+config CAVS_ISR_TBL_OFFSET
+ default 2ND_LVL_ISR_TBL_OFFSET
+
+config DMA_DW
+ default y
+ depends on DMA
+
+config I2S_CAVS
+ default y
+ depends on I2S
+
+endif # BOARD_INTEL_ADSP_CAVS25
diff --git a/boards/xtensa/intel_adsp_cavs25/board.cmake b/boards/xtensa/intel_adsp_cavs25/board.cmake
new file mode 100644
index 0000000..6b01bab
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs25/board.cmake
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(misc-flasher)
+board_finalize_runner_args(misc-flasher)
diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.dts b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.dts
new file mode 100644
index 0000000..d4c1cac
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <intel/intel_cavs25.dtsi>
+
+/ {
+ model = "intel_adsp_cavs25";
+ compatible = "intel";
+
+ chosen {
+ zephyr,sram = &sram0;
+ };
+};
diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.yaml b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.yaml
new file mode 100644
index 0000000..2d65f48
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.yaml
@@ -0,0 +1,9 @@
+identifier: intel_adsp_cavs25
+name: CAVS 2.5 Audio DSP (Connected Audio Voice and Speech)
+type: mcu
+arch: xtensa
+toolchain:
+ - zephyr
+testing:
+ only_tags:
+ - kernel
diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig
new file mode 100644
index 0000000..d762d26
--- /dev/null
+++ b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+
+CONFIG_SOC_SERIES_INTEL_CAVS_V25=y
+CONFIG_BOARD_INTEL_ADSP_CAVS25=y
+
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+
+CONFIG_XTENSA_RESET_VECTOR=y
+
+CONFIG_XTENSA_USE_CORE_CRT1=y
+
+CONFIG_MULTI_LEVEL_INTERRUPTS=y
+CONFIG_2ND_LEVEL_INTERRUPTS=y
+CONFIG_CAVS_ICTL=y
+
+CONFIG_BOOTLOADER_SRAM_SIZE=192
diff --git a/boards/xtensa/intel_s1000_crb/Kconfig.defconfig b/boards/xtensa/intel_s1000_crb/Kconfig.defconfig
index 4c16d44..4363039 100644
--- a/boards/xtensa/intel_s1000_crb/Kconfig.defconfig
+++ b/boards/xtensa/intel_s1000_crb/Kconfig.defconfig
@@ -45,10 +45,6 @@
config DW_ISR_TBL_OFFSET
default 3RD_LVL_ISR_TBL_OFFSET
-config HEAP_MEM_POOL_SIZE
- default 1024
- depends on DMA_DW
-
config ROM_START_OFFSET
default 0x100
depends on BOOTLOADER_MCUBOOT
diff --git a/boards/xtensa/up_squared_adsp/Kconfig.board b/boards/xtensa/up_squared_adsp/Kconfig.board
index 0f443f7..a7742e2 100644
--- a/boards/xtensa/up_squared_adsp/Kconfig.board
+++ b/boards/xtensa/up_squared_adsp/Kconfig.board
@@ -5,4 +5,4 @@
config BOARD_UP_SQUARED_ADSP
bool "Xtensa on Up Squared"
- depends on SOC_INTEL_APL_ADSP
+ depends on SOC_SERIES_INTEL_CAVS_V15
diff --git a/boards/xtensa/up_squared_adsp/Kconfig.defconfig b/boards/xtensa/up_squared_adsp/Kconfig.defconfig
index dc1a199..8cc322c 100644
--- a/boards/xtensa/up_squared_adsp/Kconfig.defconfig
+++ b/boards/xtensa/up_squared_adsp/Kconfig.defconfig
@@ -35,10 +35,6 @@
config CAVS_ISR_TBL_OFFSET
default 2ND_LVL_ISR_TBL_OFFSET
-config HEAP_MEM_POOL_SIZE
- default 1024
- depends on DMA_DW
-
config DMA_DW
default y
depends on DMA
diff --git a/boards/xtensa/up_squared_adsp/tools/adsplog.py b/boards/xtensa/up_squared_adsp/tools/adsplog.py
new file mode 100755
index 0000000..0a2a182
--- /dev/null
+++ b/boards/xtensa/up_squared_adsp/tools/adsplog.py
@@ -0,0 +1,84 @@
+#!/usr/bin/python3
+#
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+import sys
+import time
+import struct
+import subprocess
+import mmap
+
+MAP_SIZE = 8192
+SLOT_SIZE = 64
+
+# Location of the log output window within the mapping of the SRAM
+# (BAR4) on the PCI device. These numbers are cribbed from existing
+# scripting, I don't know what they really mean or where the spec for
+# these protocols is. The driver on the DSP just hard codes an
+# address.
+WIN_OFFSET = 0x80000
+WIN_ID = 3
+WIN_SIZE = 0x20000
+LOG_OFFSET = WIN_OFFSET + WIN_ID * WIN_SIZE
+
+# Find me a way to do this detection as cleanly in python as shell, I
+# dare you.
+barfile = subprocess.Popen(["sh", "-c",
+ "echo -n "
+ "$(dirname "
+ " $(fgrep PCI_ID=8086:5A98 "
+ " /sys/bus/pci/devices/*/uevent))"
+ "/resource4"],
+ stdout=subprocess.PIPE).stdout.read()
+fd = open(barfile)
+mem = mmap.mmap(fd.fileno(), MAP_SIZE, offset=LOG_OFFSET,
+ prot=mmap.PROT_READ)
+
+# The mapping is an array of 64-byte "slots", each of which is
+# prefixed by a magic number, which should be 0x55aa for log data,
+# followed a 16 bit "ID" number, followed by a null-terminated string
+# in the final 60 bytes. The DSP firmware will write sequential IDs
+# into the buffer starting from an ID of zero in the first slot, and
+# wrapping at the end. So the algorithm here is to find the smallest
+# valid slot, print its data, and then enter a polling loop waiting
+# for the next slot to be valid and have the correct next ID before
+# printing that too.
+
+# NOTE: unfortunately there's no easy way to detect a warm reset of
+# the device, it will just jump back to the beginning and start
+# writing there, where we aren't looking. Really that level of
+# robustness needs to be handled in the kernel.
+
+next_slot = 0
+next_id = 0xffff
+
+for slot in range(int(MAP_SIZE / SLOT_SIZE)):
+ off = slot * SLOT_SIZE
+ (magic, sid) = struct.unpack("HH", mem[off:off+4])
+ if magic == 0x55aa:
+ if sid < next_id:
+ next_slot = slot
+ next_id = sid
+
+while True:
+ off = next_slot * SLOT_SIZE
+ (magic, sid) = struct.unpack("HH", mem[off:off+4])
+ if magic == 0x55aa and sid == next_id:
+ # This dance because indexing large variable-length slices of
+ # the mmap() array seems to produce garbage....
+ msgbytes = []
+ for i in range(4, SLOT_SIZE):
+ b = mem[off+i]
+ if b == 0:
+ break
+ msgbytes.append(b)
+ msg = bytearray(len(msgbytes))
+ for i in range(len(msgbytes)):
+ msg[i] = msgbytes[i]
+
+ sys.stdout.write(msg.decode(encoding="utf-8", errors="ignore"))
+ next_slot = int((next_slot + 1) % (MAP_SIZE / SLOT_SIZE))
+ next_id += 1
+ else:
+ sys.stdout.flush()
+ time.sleep(0.25)
diff --git a/boards/xtensa/up_squared_adsp/tools/lib/loglist.py b/boards/xtensa/up_squared_adsp/tools/lib/loglist.py
index 082531a..a2468ab 100644
--- a/boards/xtensa/up_squared_adsp/tools/lib/loglist.py
+++ b/boards/xtensa/up_squared_adsp/tools/lib/loglist.py
@@ -16,12 +16,11 @@
class Loglist:
"""Loglist class"""
- def __init__(self, argument, debug=False, offset=0):
+ def __init__(self, argument, debug=False):
"""Constructor for the loglist takes argument filename or buffer"""
if isinstance(argument, str):
f = open(argument, "rb")
- f.seek(offset)
self.buffer = f.read(SLOT_NUM * SLOT_LEN)
elif isinstance(argument, int):
self.buffer = string_at(argument, SLOT_NUM * SLOT_LEN)
diff --git a/boards/xtensa/up_squared_adsp/tools/logtool.py b/boards/xtensa/up_squared_adsp/tools/logtool.py
index cceb523..9c0609f 100755
--- a/boards/xtensa/up_squared_adsp/tools/logtool.py
+++ b/boards/xtensa/up_squared_adsp/tools/logtool.py
@@ -42,12 +42,10 @@
else:
if args.etrace == 'sof':
etrace = SOF_ETRACE
- offset = 0
else:
etrace = QEMU_ETRACE
- offset = 0x8000
- l = Loglist(etrace, offset=offset)
+ l = Loglist(etrace)
l.print()
if __name__ == "__main__":
diff --git a/boards/xtensa/up_squared_adsp/tools/up_squared_adsp_flash.sh b/boards/xtensa/up_squared_adsp/tools/up_squared_adsp_flash.sh
deleted file mode 100755
index 1ee9451..0000000
--- a/boards/xtensa/up_squared_adsp/tools/up_squared_adsp_flash.sh
+++ /dev/null
@@ -1,18 +0,0 @@
-#!/bin/sh
-# Copyright (c) 2020 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-BUILD=$1
-FIRMWARE=${BUILD}/zephyr/zephyr.ri
-FLASHER=${ZEPHYR_BASE}/boards/xtensa/up_squared_adsp/tools/fw_loader.py
-
-if [ -z "$2" ]
- then
- echo "Signing using default key"
- west sign -d ${BUILD} -t rimage
-else
- echo "Signing with key " $key
- west sign -d ${BUILD} -t rimage -- -k $2
-fi
-
-${FLASHER} -f ${FIRMWARE} 2>&1
diff --git a/boards/xtensa/up_squared_adsp/up_squared_adsp.dts b/boards/xtensa/up_squared_adsp/up_squared_adsp.dts
index b328d67..859368d 100644
--- a/boards/xtensa/up_squared_adsp/up_squared_adsp.dts
+++ b/boards/xtensa/up_squared_adsp/up_squared_adsp.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include <intel/intel_apl_adsp.dtsi>
+#include <intel/intel_cavs15.dtsi>
/ {
model = "up_squared_adsp";
diff --git a/boards/xtensa/up_squared_adsp/up_squared_adsp.yaml b/boards/xtensa/up_squared_adsp/up_squared_adsp.yaml
index f708860..5fb4195 100644
--- a/boards/xtensa/up_squared_adsp/up_squared_adsp.yaml
+++ b/boards/xtensa/up_squared_adsp/up_squared_adsp.yaml
@@ -5,5 +5,5 @@
toolchain:
- zephyr
testing:
- ignore_tags:
- - net
+ only_tags:
+ - kernel
diff --git a/boards/xtensa/up_squared_adsp/up_squared_adsp_defconfig b/boards/xtensa/up_squared_adsp/up_squared_adsp_defconfig
index 7446909..6d4769e 100644
--- a/boards/xtensa/up_squared_adsp/up_squared_adsp_defconfig
+++ b/boards/xtensa/up_squared_adsp/up_squared_adsp_defconfig
@@ -2,7 +2,7 @@
CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_SOC_INTEL_APL_ADSP=y
+CONFIG_SOC_SERIES_INTEL_CAVS_V15=y
CONFIG_BOARD_UP_SQUARED_ADSP=y
CONFIG_GEN_ISR_TABLES=y
diff --git a/cmake/toolchain/zephyr/0.11/target.cmake b/cmake/toolchain/zephyr/0.11/target.cmake
index 78b463c..7d96850 100644
--- a/cmake/toolchain/zephyr/0.11/target.cmake
+++ b/cmake/toolchain/zephyr/0.11/target.cmake
@@ -16,9 +16,26 @@
set(SYSROOT_TARGET ${CROSS_COMPILE_TARGET})
if("${ARCH}" STREQUAL "xtensa")
- set(SYSROOT_DIR ${TOOLCHAIN_HOME}/xtensa/${SOC_NAME}/${SYSROOT_TARGET})
- set(CROSS_COMPILE ${TOOLCHAIN_HOME}/xtensa/${SOC_NAME}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
+ # Xtensa GCC needs a different toolchain per SOC
+ if("${SOC_SERIES}" STREQUAL "cavs_v15")
+ set(SR_XT_TC_SOC intel_apl_adsp)
+ elseif("${SOC_SERIES}" STREQUAL "cavs_v18")
+ set(SR_XT_TC_SOC intel_s1000)
+ elseif("${SOC_SERIES}" STREQUAL "cavs_v20")
+ set(SR_XT_TC_SOC intel_s1000)
+ elseif("${SOC_SERIES}" STREQUAL "cavs_v25")
+ set(SR_XT_TC_SOC intel_s1000)
+ elseif("${SOC_SERIES}" STREQUAL "baytrail_adsp")
+ set(SR_XT_TC_SOC intel_byt_adsp)
+ elseif("${SOC_SERIES}" STREQUAL "broadwell_adsp")
+ set(SR_XT_TC_SOC intel_bdw_adsp)
+ else()
+ message(FATAL_ERROR "Not compiler set for SOC_SERIES ${SOC_SERIES}")
+ endif()
+ set(SYSROOT_DIR ${TOOLCHAIN_HOME}/xtensa/${SR_XT_TC_SOC}/${SYSROOT_TARGET})
+ set(CROSS_COMPILE ${TOOLCHAIN_HOME}/xtensa/${SR_XT_TC_SOC}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
else()
+ # Non-Xtensa SDK toolchains follow a simpler convention
set(SYSROOT_DIR ${TOOLCHAIN_HOME}/${SYSROOT_TARGET}/${SYSROOT_TARGET})
set(CROSS_COMPILE ${TOOLCHAIN_HOME}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
endif()
diff --git a/drivers/interrupt_controller/intc_cavs.c b/drivers/interrupt_controller/intc_cavs.c
index 5cc46a2..0cc9105 100644
--- a/drivers/interrupt_controller/intc_cavs.c
+++ b/drivers/interrupt_controller/intc_cavs.c
@@ -13,7 +13,7 @@
#if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 1)
#if defined(CONFIG_SOC_INTEL_S1000)
#define PER_CPU_OFFSET(x) (0x40 * x)
-#elif defined(CONFIG_SOC_INTEL_APL_ADSP)
+#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
#define PER_CPU_OFFSET(x) (0x40 * x)
#else
#error "Must define PER_CPU_OFFSET(x) for SoC"
diff --git a/dts/xtensa/intel/intel_byt_adsp.dtsi b/dts/xtensa/intel/intel_byt_adsp.dtsi
new file mode 100644
index 0000000..fd24610
--- /dev/null
+++ b/dts/xtensa/intel/intel_byt_adsp.dtsi
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2019 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <xtensa/xtensa.dtsi>
+#include <dt-bindings/i2c/i2c.h>
+#include <mem.h>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "cadence,tensilica-xtensa-lx4";
+ reg = <0>;
+ };
+ };
+
+ sram0: memory@FF2C0000 {
+ device_type = "memory";
+ compatible = "mmio-sram";
+ reg = <0xFF2C0000 DT_SIZE_K(96)>;
+ };
+
+ sram1: memory@FF300000 {
+ device_type = "memory";
+ compatible = "mmio-sram";
+ reg = <0xFF300000 DT_SIZE_K(168)>;
+ };
+
+ soc {
+
+ core_intc: core_intc@0 {
+ compatible = "xtensa,core-intc";
+ reg = <0x00 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ mailbox: mailbox@ff340018 {
+ compatible = "intel,intel-adsp-mailbox";
+ reg = <0xFF340018 0x30>;
+ interrupts = <0x7 0 3>;
+ interrupt-parent = <&core_intc>;
+ label = "IPM_0";
+ };
+ };
+};
diff --git a/dts/xtensa/intel/intel_apl_adsp.dtsi b/dts/xtensa/intel/intel_cavs15.dtsi
similarity index 91%
rename from dts/xtensa/intel/intel_apl_adsp.dtsi
rename to dts/xtensa/intel/intel_cavs15.dtsi
index 6157910..b8567ce 100644
--- a/dts/xtensa/intel/intel_apl_adsp.dtsi
+++ b/dts/xtensa/intel/intel_cavs15.dtsi
@@ -104,5 +104,13 @@
compatible = "zephyr,ipm-console";
label="IPM_0";
};
+
+ mailbox: mailbox@1180 {
+ compatible = "intel,intel-adsp-mailbox";
+ reg = <0x1180 0x20>;
+ interrupts = <0x7 0 3>;
+ interrupt-parent = <&cavs0>;
+ label = "IPM_0";
+ };
};
};
diff --git a/dts/xtensa/intel/intel_apl_adsp.dtsi b/dts/xtensa/intel/intel_cavs18.dtsi
similarity index 74%
copy from dts/xtensa/intel/intel_apl_adsp.dtsi
copy to dts/xtensa/intel/intel_cavs18.dtsi
index 6157910..c5ca9fd 100644
--- a/dts/xtensa/intel/intel_apl_adsp.dtsi
+++ b/dts/xtensa/intel/intel_cavs18.dtsi
@@ -24,14 +24,28 @@
compatible = "cadence,tensilica-xtensa-lx4";
reg = <1>;
};
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "cadence,tensilica-xtensa-lx4";
+ reg = <2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "cadence,tensilica-xtensa-lx4";
+ reg = <3>;
+ };
};
sram0: memory@be000000 {
+ device_type = "memory";
compatible = "mmio-sram";
- reg = <0xbe000000 DT_SIZE_K(512)>;
+ reg = <0xbe000000 DT_SIZE_K(3008)>;
};
sram1: memory@be800000 {
+ device_type = "memory";
compatible = "mmio-sram";
reg = <0xbe800000 DT_SIZE_K(128)>;
};
@@ -44,9 +58,9 @@
#interrupt-cells = <3>;
};
- cavs0: cavs@1600 {
+ cavs0: cavs@78800 {
compatible = "intel,cavs-intc";
- reg = <0x1600 0x10>;
+ reg = <0x78800 0x10>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <6 0 0>;
@@ -54,9 +68,9 @@
label = "CAVS_0";
};
- cavs1: cavs@1610 {
+ cavs1: cavs@78810 {
compatible = "intel,cavs-intc";
- reg = <0x1610 0x10>;
+ reg = <0x78810 0x10>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0xA 0 0>;
@@ -64,9 +78,9 @@
label = "CAVS_1";
};
- cavs2: cavs@1620 {
+ cavs2: cavs@78820 {
compatible = "intel,cavs-intc";
- reg = <0x1620 0x10>;
+ reg = <0x78820 0x10>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0XD 0 0>;
@@ -74,9 +88,9 @@
label = "CAVS_2";
};
- cavs3: cavs@1630 {
+ cavs3: cavs@78830 {
compatible = "intel,cavs-intc";
- reg = <0x1630 0x10>;
+ reg = <0x78830 0x10>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0x10 0 0>;
@@ -90,19 +104,13 @@
reg = <0x1200 0x80>;
interrupts = <8 0 0>;
interrupt-parent = <&cavs0>;
- };
-
- mailbox: mailbox@1180 {
- compatible = "intel,adsp-mailbox";
- reg = <0x1180 0x20>;
+ };
+ mailbox: mailbox@71e00 {
+ compatible = "intel,intel-adsp-mailbox";
+ reg = <0x71E00 0x20>;
interrupts = <0x7 0 3>;
interrupt-parent = <&cavs0>;
label = "IPM_0";
};
-
- ipm_console: ipm_console {
- compatible = "zephyr,ipm-console";
- label="IPM_0";
- };
};
};
diff --git a/dts/xtensa/intel/intel_apl_adsp.dtsi b/dts/xtensa/intel/intel_cavs20.dtsi
similarity index 74%
copy from dts/xtensa/intel/intel_apl_adsp.dtsi
copy to dts/xtensa/intel/intel_cavs20.dtsi
index 6157910..c5ca9fd 100644
--- a/dts/xtensa/intel/intel_apl_adsp.dtsi
+++ b/dts/xtensa/intel/intel_cavs20.dtsi
@@ -24,14 +24,28 @@
compatible = "cadence,tensilica-xtensa-lx4";
reg = <1>;
};
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "cadence,tensilica-xtensa-lx4";
+ reg = <2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "cadence,tensilica-xtensa-lx4";
+ reg = <3>;
+ };
};
sram0: memory@be000000 {
+ device_type = "memory";
compatible = "mmio-sram";
- reg = <0xbe000000 DT_SIZE_K(512)>;
+ reg = <0xbe000000 DT_SIZE_K(3008)>;
};
sram1: memory@be800000 {
+ device_type = "memory";
compatible = "mmio-sram";
reg = <0xbe800000 DT_SIZE_K(128)>;
};
@@ -44,9 +58,9 @@
#interrupt-cells = <3>;
};
- cavs0: cavs@1600 {
+ cavs0: cavs@78800 {
compatible = "intel,cavs-intc";
- reg = <0x1600 0x10>;
+ reg = <0x78800 0x10>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <6 0 0>;
@@ -54,9 +68,9 @@
label = "CAVS_0";
};
- cavs1: cavs@1610 {
+ cavs1: cavs@78810 {
compatible = "intel,cavs-intc";
- reg = <0x1610 0x10>;
+ reg = <0x78810 0x10>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0xA 0 0>;
@@ -64,9 +78,9 @@
label = "CAVS_1";
};
- cavs2: cavs@1620 {
+ cavs2: cavs@78820 {
compatible = "intel,cavs-intc";
- reg = <0x1620 0x10>;
+ reg = <0x78820 0x10>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0XD 0 0>;
@@ -74,9 +88,9 @@
label = "CAVS_2";
};
- cavs3: cavs@1630 {
+ cavs3: cavs@78830 {
compatible = "intel,cavs-intc";
- reg = <0x1630 0x10>;
+ reg = <0x78830 0x10>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0x10 0 0>;
@@ -90,19 +104,13 @@
reg = <0x1200 0x80>;
interrupts = <8 0 0>;
interrupt-parent = <&cavs0>;
- };
-
- mailbox: mailbox@1180 {
- compatible = "intel,adsp-mailbox";
- reg = <0x1180 0x20>;
+ };
+ mailbox: mailbox@71e00 {
+ compatible = "intel,intel-adsp-mailbox";
+ reg = <0x71E00 0x20>;
interrupts = <0x7 0 3>;
interrupt-parent = <&cavs0>;
label = "IPM_0";
};
-
- ipm_console: ipm_console {
- compatible = "zephyr,ipm-console";
- label="IPM_0";
- };
};
};
diff --git a/dts/xtensa/intel/intel_apl_adsp.dtsi b/dts/xtensa/intel/intel_cavs25.dtsi
similarity index 74%
copy from dts/xtensa/intel/intel_apl_adsp.dtsi
copy to dts/xtensa/intel/intel_cavs25.dtsi
index 6157910..c5ca9fd 100644
--- a/dts/xtensa/intel/intel_apl_adsp.dtsi
+++ b/dts/xtensa/intel/intel_cavs25.dtsi
@@ -24,14 +24,28 @@
compatible = "cadence,tensilica-xtensa-lx4";
reg = <1>;
};
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "cadence,tensilica-xtensa-lx4";
+ reg = <2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "cadence,tensilica-xtensa-lx4";
+ reg = <3>;
+ };
};
sram0: memory@be000000 {
+ device_type = "memory";
compatible = "mmio-sram";
- reg = <0xbe000000 DT_SIZE_K(512)>;
+ reg = <0xbe000000 DT_SIZE_K(3008)>;
};
sram1: memory@be800000 {
+ device_type = "memory";
compatible = "mmio-sram";
reg = <0xbe800000 DT_SIZE_K(128)>;
};
@@ -44,9 +58,9 @@
#interrupt-cells = <3>;
};
- cavs0: cavs@1600 {
+ cavs0: cavs@78800 {
compatible = "intel,cavs-intc";
- reg = <0x1600 0x10>;
+ reg = <0x78800 0x10>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <6 0 0>;
@@ -54,9 +68,9 @@
label = "CAVS_0";
};
- cavs1: cavs@1610 {
+ cavs1: cavs@78810 {
compatible = "intel,cavs-intc";
- reg = <0x1610 0x10>;
+ reg = <0x78810 0x10>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0xA 0 0>;
@@ -64,9 +78,9 @@
label = "CAVS_1";
};
- cavs2: cavs@1620 {
+ cavs2: cavs@78820 {
compatible = "intel,cavs-intc";
- reg = <0x1620 0x10>;
+ reg = <0x78820 0x10>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0XD 0 0>;
@@ -74,9 +88,9 @@
label = "CAVS_2";
};
- cavs3: cavs@1630 {
+ cavs3: cavs@78830 {
compatible = "intel,cavs-intc";
- reg = <0x1630 0x10>;
+ reg = <0x78830 0x10>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0x10 0 0>;
@@ -90,19 +104,13 @@
reg = <0x1200 0x80>;
interrupts = <8 0 0>;
interrupt-parent = <&cavs0>;
- };
-
- mailbox: mailbox@1180 {
- compatible = "intel,adsp-mailbox";
- reg = <0x1180 0x20>;
+ };
+ mailbox: mailbox@71e00 {
+ compatible = "intel,intel-adsp-mailbox";
+ reg = <0x71E00 0x20>;
interrupts = <0x7 0 3>;
interrupt-parent = <&cavs0>;
label = "IPM_0";
};
-
- ipm_console: ipm_console {
- compatible = "zephyr,ipm-console";
- label="IPM_0";
- };
};
};
diff --git a/soc/xtensa/CMakeLists.txt b/soc/xtensa/CMakeLists.txt
new file mode 100644
index 0000000..b826da9
--- /dev/null
+++ b/soc/xtensa/CMakeLists.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(SOC_FAMILY)
+ add_subdirectory(${SOC_FAMILY})
+else()
+ add_subdirectory(${SOC_NAME})
+endif()
diff --git a/soc/xtensa/intel_apl_adsp/common/CMakeLists.txt b/soc/xtensa/intel_adsp/CMakeLists.txt
similarity index 81%
rename from soc/xtensa/intel_apl_adsp/common/CMakeLists.txt
rename to soc/xtensa/intel_adsp/CMakeLists.txt
index d1ca770..d5989ca 100644
--- a/soc/xtensa/intel_apl_adsp/common/CMakeLists.txt
+++ b/soc/xtensa/intel_adsp/CMakeLists.txt
@@ -3,4 +3,4 @@
# Copyright (c) 2020 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
-include(bootloader.cmake)
+add_subdirectory(common)
diff --git a/soc/xtensa/intel_adsp/Kconfig b/soc/xtensa/intel_adsp/Kconfig
new file mode 100644
index 0000000..65d29b8
--- /dev/null
+++ b/soc/xtensa/intel_adsp/Kconfig
@@ -0,0 +1,18 @@
+# Intel CAVS SoC family configuration options
+#
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_INTEL_ADSP
+ bool
+
+if SOC_FAMILY_INTEL_ADSP
+
+config SOC_FAMILY
+ string
+ default "intel_adsp"
+
+# Select SoC Part No. and configuration options
+source "soc/xtensa/intel_adsp/*/Kconfig.soc"
+
+endif # SOC_FAMILY_INTEL_ADSP
diff --git a/soc/xtensa/intel_adsp/Kconfig.defconfig b/soc/xtensa/intel_adsp/Kconfig.defconfig
new file mode 100644
index 0000000..76b0605
--- /dev/null
+++ b/soc/xtensa/intel_adsp/Kconfig.defconfig
@@ -0,0 +1,6 @@
+# Intel CAVS SoC family default configuration options
+#
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/xtensa/intel_adsp/*/Kconfig.defconfig.series"
diff --git a/soc/xtensa/intel_adsp/Kconfig.soc b/soc/xtensa/intel_adsp/Kconfig.soc
new file mode 100644
index 0000000..448b164
--- /dev/null
+++ b/soc/xtensa/intel_adsp/Kconfig.soc
@@ -0,0 +1,6 @@
+# Intel CAVS SoC series selection
+#
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/xtensa/intel_adsp/*/Kconfig.series"
diff --git a/soc/xtensa/intel_apl_adsp/Kconfig.defconfig b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series
similarity index 67%
copy from soc/xtensa/intel_apl_adsp/Kconfig.defconfig
copy to soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series
index f439ab6..8cfbb05 100644
--- a/soc/xtensa/intel_apl_adsp/Kconfig.defconfig
+++ b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series
@@ -1,23 +1,37 @@
-# Xtensa board configuration
-
-# Copyright (c) 2017 Intel Corporation
+# Copyright (c) 2020 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
-if SOC_INTEL_APL_ADSP
+if SOC_SERIES_INTEL_CAVS_V15
+
+config SOC_SERIES
+ string
+ default "cavs_v15"
config SOC
string
- default "intel_apl_adsp"
+ default "intel_apl_adsp" if SOC_INTEL_CAVS_APL
+
+config MP_NUM_CPUS
+ default 2
+
+config XTENSA_TIMER
+ default n
+
+config CAVS_TIMER
+ default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 400000000 if XTENSA_TIMER
default 19200000 if CAVS_TIMER
+config SYS_CLOCK_TICKS_PER_SEC
+ default 50000
+
config IRQ_OFFLOAD_INTNUM
default 0
-# S1000 does not have MISC0.
-# Since EXCSAVE2 is unused by Zephyr, use it instead.
+# This series does not have MISC0.
+# Since EXCSAVE7 is unused by Zephyr, use it instead.
config XTENSA_KERNEL_CPU_PTR_SR
default "EXCSAVE2"
@@ -41,17 +55,22 @@
default n
depends on TEST
+config IPM_CAVS_IDC
+ default y
+
+config IPM
+ default y
+
if LOG
-# When console is enabled printk should go through it
config LOG_PRINTK
- default y if !CONSOLE
+ default y
config LOG_BACKEND_RB
default y
config LOG_BACKEND_RB_MEM_BASE
- default 0xBE008000
+ default 0xBE000000
config LOG_BACKEND_RB_MEM_SIZE
default 8192
@@ -60,33 +79,9 @@
if SMP
-config MP_NUM_CPUS
- default 2
-
-config XTENSA_TIMER
- default n
-
-config CAVS_TIMER
- default y
-
-config IPM
- default y
-
-config IPM_CAVS_IDC
- default y if IPM
-
config SCHED_IPI_SUPPORTED
default y if IPM_CAVS_IDC
-endif
+endif # SMP
-config IPM_INTEL_ADSP
- default y
- depends on IPM
-
-config IPM_CONSOLE
- default y
- depends on CONSOLE
- depends on IPM
-
-endif
+endif # SOC_SERIES_INTEL_CAVS_V15
diff --git a/soc/xtensa/intel_apl_adsp/Kconfig.soc b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.series
similarity index 68%
rename from soc/xtensa/intel_apl_adsp/Kconfig.soc
rename to soc/xtensa/intel_adsp/cavs_v15/Kconfig.series
index 2a76ea8..50182b2 100644
--- a/soc/xtensa/intel_apl_adsp/Kconfig.soc
+++ b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.series
@@ -1,10 +1,13 @@
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
-config SOC_INTEL_APL_ADSP
- bool "intel_apl_adsp"
+config SOC_SERIES_INTEL_CAVS_V15
+ bool "Intel CAVS v1.5"
+ select SOC_FAMILY_INTEL_ADSP
select XTENSA
select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
select XTENSA_RESET_VECTOR
select XTENSA_USE_CORE_CRT1
select ATOMIC_OPERATIONS_BUILTIN
+ help
+ Intel CAVS v1.5
diff --git a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.soc b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.soc
new file mode 100644
index 0000000..d9d4885
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.soc
@@ -0,0 +1,11 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+ prompt "Intel CAVS SoC Selection"
+
+ config SOC_INTEL_CAVS_APL
+ bool "Apollo Lake"
+ depends on SOC_SERIES_INTEL_CAVS_V15
+
+endchoice
diff --git a/soc/xtensa/intel_apl_adsp/include/_soc_inthandlers.h b/soc/xtensa/intel_adsp/cavs_v15/include/_soc_inthandlers.h
similarity index 100%
rename from soc/xtensa/intel_apl_adsp/include/_soc_inthandlers.h
rename to soc/xtensa/intel_adsp/cavs_v15/include/_soc_inthandlers.h
diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
new file mode 100644
index 0000000..41c028b
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2019 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_MEMORY_H
+#define __INC_MEMORY_H
+
+/* L2 HP SRAM */
+#define HP_RAM_RESERVE_HEADER_SPACE (HP_SRAM_WIN0_SIZE + \
+ SRAM_INBOX_SIZE + \
+ SRAM_STREAM_SIZE + \
+ SRAM_EXCEPT_SIZE + \
+ SRAM_DEBUG_SIZE + \
+ SRAM_TRACE_SIZE)
+
+#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
+#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
+
+#ifdef CONFIG_BOOTLOADER_MCUBOOT
+#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
+#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
+#else
+#define SRAM_BASE (L2_SRAM_BASE)
+#define SRAM_SIZE (L2_SRAM_SIZE)
+#endif
+
+/* The reset vector address in SRAM and its size */
+#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE
+#define MEM_RESET_TEXT_SIZE 0x268
+#define MEM_RESET_LIT_SIZE 0x8
+
+/* This is the base address of all the vectors defined in SRAM */
+#define XCHAL_VECBASE_RESET_PADDR_SRAM \
+ (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE)
+
+#define MEM_VECBASE_LIT_SIZE 0x178
+
+/* The addresses of the vectors in SRAM.
+ * Only the memerror vector continues to point to its ROM address.
+ */
+#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x180)
+
+#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x1C0)
+
+#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x200)
+
+#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x240)
+
+#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x280)
+
+#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x2C0)
+
+#define XCHAL_KERNEL_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x300)
+
+#define XCHAL_USER_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x340)
+
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x3C0)
+
+#define VECTOR_TBL_SIZE 0x0400
+
+/* Vector and literal sizes */
+#define MEM_VECT_LIT_SIZE 0x8
+#define MEM_VECT_TEXT_SIZE 0x38
+#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
+ MEM_VECT_LIT_SIZE)
+
+#define MEM_ERROR_TEXT_SIZE 0x180
+#define MEM_ERROR_LIT_SIZE 0x8
+
+/* text and data share the same L2 HP SRAM.
+ * So, they lie next to each other.
+ */
+#define RAM_BASE \
+ (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
+
+#define RAM_SIZE \
+ (SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
+
+#define LPSRAM_MASK(x) 0x00000003
+
+/* Location for the intList section which is later used to construct the
+ * Interrupt Descriptor Table (IDT). This is a bogus address as this
+ * section will be stripped off in the final image.
+ */
+#define IDT_BASE (RAM_BASE + RAM_SIZE)
+
+/* size of the Interrupt Descriptor Table (IDT) */
+#define IDT_SIZE 0x2000
+
+/* low power ram where DMA buffers are typically placed */
+#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
+#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
+
+/* bootloader */
+
+#define HP_SRAM_BASE 0xbe000000
+#define HP_SRAM_SIZE (512 * 1024)
+#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
+
+/* boot loader in IMR */
+#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB000A000
+#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120
+
+#define IMR_BOOT_LDR_LIT_BASE \
+ (IMR_BOOT_LDR_TEXT_ENTRY_BASE + IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
+#define IMR_BOOT_LDR_LIT_SIZE 0x100
+
+#define IMR_BOOT_LDR_TEXT_BASE \
+ (IMR_BOOT_LDR_LIT_BASE + IMR_BOOT_LDR_LIT_SIZE)
+#define IMR_BOOT_LDR_TEXT_SIZE 0x1c00
+
+#define IMR_BOOT_LDR_DATA_BASE 0xb0002000
+#define IMR_BOOT_LDR_DATA_SIZE 0x1000
+
+#define IMR_BOOT_LDR_BSS_BASE 0xb0100000
+#define IMR_BOOT_LDR_BSS_SIZE 0x10000
+
+#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \
+ BOOT_LDR_STACK_SIZE)
+#define BOOT_LDR_STACK_SIZE (4 * 0x1000)
+
+/* Manifest base address in IMR - used by boot loader copy procedure. */
+#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000
+
+/* Manifest size (seems unused). */
+#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000
+
+
+#define UUID_ENTRY_ELF_BASE 0x1FFFA000
+#define UUID_ENTRY_ELF_SIZE 0x6000
+
+#define LOG_ENTRY_ELF_BASE 0x20000000
+#define LOG_ENTRY_ELF_SIZE 0x2000000
+
+
+#define SRAM_ALIAS_BASE 0x9E000000
+#define SRAM_ALIAS_MASK 0xFF000000
+#define SRAM_ALIAS_OFFSET 0x20000000
+
+
+#define uncache_to_cache(address) \
+ ((__typeof__((address)))((uint32_t)((address)) + SRAM_ALIAS_OFFSET))
+#define cache_to_uncache(address) \
+ ((__typeof__((address)))((uint32_t)((address)) - SRAM_ALIAS_OFFSET))
+#define is_uncached(address) \
+ (((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_ALIAS_BASE)
+
+/* shim */
+#define SHIM_BASE 0x00001000
+#define SHIM_SIZE 0x00000100
+
+/* IRQ controller */
+#define IRQ_BASE 0x00001600
+#define IRQ_SIZE 0x00000200
+
+/* IPC to the host */
+#define IPC_HOST_BASE 0x00001180
+#define IPC_HOST_SIZE 0x00000020
+
+/* intra DSP IPC */
+#define IPC_DSP_SIZE 0x00000080
+#define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE)
+
+/* SRAM window for HOST */
+#define HOST_WIN_SIZE 0x00000008
+#define HOST_WIN_BASE(x) (0x00001580 + x * HOST_WIN_SIZE)
+
+/* HP SRAM windows */
+
+/* window 3 */
+#define SRAM_TRACE_BASE 0xbe000000
+#define SRAM_TRACE_SIZE 0x2000
+
+#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE
+#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
+
+/* window 2 */
+#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE)
+#define SRAM_DEBUG_SIZE 0x800
+
+#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
+#define SRAM_EXCEPT_SIZE 0x800
+
+#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
+#define SRAM_STREAM_SIZE 0x1000
+
+/* window 1 */
+#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
+#define SRAM_INBOX_SIZE 0x2000
+
+/* window 0 */
+#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
+#define SRAM_SW_REG_SIZE 0x1000
+
+#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
+#define SRAM_OUTBOX_SIZE 0x1000
+
+#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE
+#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE)
+
+#define SOF_TEXT_START (HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE + \
+ VECTOR_TBL_SIZE)
+
+#define SOF_TEXT_BASE SOF_TEXT_START
+
+#define SRAM_REG_FW_END 0x14
+
+/* Host page size */
+#define HOST_PAGE_SIZE 4096
+
+#endif /* __INC_MEMORY_H */
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/platform.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/platform.h
similarity index 63%
rename from soc/xtensa/intel_apl_adsp/include/platform/platform.h
rename to soc/xtensa/intel_adsp/cavs_v15/include/soc/platform.h
index 95fa5ac..91dc182 100644
--- a/soc/xtensa/intel_apl_adsp/include/platform/platform.h
+++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/platform.h
@@ -10,15 +10,11 @@
#ifndef __PLATFORM_PLATFORM_H__
#define __PLATFORM_PLATFORM_H__
-#include <xtensa/config/core.h>
-
-#include <platform/memory.h>
-
#define PLATFORM_RESET_MHE_AT_BOOT 1
#define PLATFORM_DISABLE_L2CACHE_AT_BOOT 1
-#define PLATFORM_MASTER_CORE_ID 0
+#define PLATFORM_PRIMARY_CORE_ID 0
#define MAX_CORE_COUNT 2
@@ -26,15 +22,4 @@
#error "Invalid core count - exceeding core limit"
#endif
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-#include <platform/mailbox.h>
-#include <platform/io.h>
-#include <platform/shim.h>
-
-/* Host page size */
-#define HOST_PAGE_SIZE 4096
-
-#endif /* !defined(__ASSEMBLER__) && !defined(LINKER) */
-
#endif /* __PLATFORM_PLATFORM_H__ */
diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h
new file mode 100644
index 0000000..2338f91a
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h
@@ -0,0 +1,268 @@
+/* SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ * Keyon Jie <yang.jie@linux.intel.com>
+ */
+
+#ifndef __PLATFORM_LIB_SHIM_H__
+#define __PLATFORM_LIB_SHIM_H__
+
+#include <sys/util.h>
+#include <soc/memory.h>
+
+#ifndef ASSEMBLY
+#include <stdint.h>
+#endif
+
+#if !defined(__ASSEMBLER__) && !defined(LINKER)
+#include <sys/sys_io.h>
+#include <arch/common/sys_io.h>
+#endif
+
+#ifndef BIT
+#define BIT(b) (1 << (b))
+#endif
+
+/* DSP IPC for Host Registers */
+#define IPC_DIPCT 0x00
+#define IPC_DIPCTE 0x04
+#define IPC_DIPCI 0x08
+#define IPC_DIPCIE 0x0c
+#define IPC_DIPCCTL 0x10
+
+/* DIPCT */
+#define IPC_DIPCT_BUSY BIT(31)
+#define IPC_DIPCT_MSG_MASK 0x7FFFFFFF
+
+/* DIPCTE */
+#define IPC_DIPCTE_MSG_MASK 0x3FFFFFFF
+
+/* DIPCI */
+#define IPC_DIPCI_BUSY BIT(31)
+#define IPC_DIPCI_MSG_MASK 0x7FFFFFFF
+
+/* DIPCIE */
+#define IPC_DIPCIE_DONE BIT(30)
+#define IPC_DIPCIE_MSG_MASK 0x3FFFFFFF
+
+/* DIPCCTL */
+#define IPC_DIPCCTL_IPCIDIE BIT(1)
+#define IPC_DIPCCTL_IPCTBIE BIT(0)
+
+#define IPC_DSP_OFFSET 0x10
+
+/* DSP IPC for intra DSP communication */
+#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET)
+#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET)
+#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET)
+#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET)
+#define IPC_IDCCTL 0x50
+
+/* IDCTFC */
+#define IPC_IDCTFC_BUSY BIT(31)
+#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF
+
+/* IDCTEFC */
+#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF
+
+/* IDCITC */
+#define IPC_IDCITC_BUSY BIT(31)
+#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF
+
+/* IDCIETC */
+#define IPC_IDCIETC_DONE BIT(30)
+#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF
+
+/* IDCCTL */
+#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x))
+#define IPC_IDCCTL_IDCTBIE(x) BIT(x)
+
+#define IRQ_CPU_OFFSET 0x40
+
+#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL2MD_ALL 0x03F181F0
+
+#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL3MD_ALL 0x807F81FF
+
+#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL4MD_ALL 0x807F81FF
+
+#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF
+
+#define REG_IRQ_IL2RSD 0x100
+#define REG_IRQ_IL3RSD 0x104
+#define REG_IRQ_IL4RSD 0x108
+#define REG_IRQ_IL5RSD 0x10c
+
+#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16)
+#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24)
+
+/* DSP Shim Registers */
+#define SHIM_DSPWC 0x20 /* DSP Wall Clock */
+#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */
+#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */
+#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */
+
+#define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */
+#define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */
+#define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */
+#define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */
+
+/** \brief Clock control */
+#define SHIM_CLKCTL 0x78
+
+/** \brief Clock status */
+#define SHIM_CLKSTS 0x7C
+
+/** \brief Request Audio PLL Clock */
+#define SHIM_CLKCTL_RAPLLC BIT(31)
+
+/** \brief Request XTAL Oscillator Clock */
+#define SHIM_CLKCTL_RXOSCC BIT(30)
+
+/** \brief Request Fast RING Oscillator Clock */
+#define SHIM_CLKCTL_RFROSCC BIT(29)
+
+/** \brief LP GPDMA Force Dynamic Clock Gating bits, 0: enable */
+#define SHIM_CLKCTL_LPGPDMAFDCGB(x) BIT(26 + x)
+
+/** \brief DMIC Force Dynamic Clock Gating */
+#define SHIM_CLKCTL_DMICFDCGB BIT(24)
+
+/** \brief I2S Force Dynamic Clock Gating */
+#define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x)
+
+/** \brief I2S Extension Force Dynamic Clock Gating */
+#define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x)
+
+/** \brief Tensilica Core Prevent Local Clock Gating */
+#define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x))
+#define SHIM_CLKCTL_TCPLCG_DIS(x) 0
+
+/** \brief Core clock PLL divisor */
+#define SHIM_CLKCTL_DPCS_MASK(x) (0x3 << (8 + x * 2))
+#define SHIM_CLKCTL_DPCS_DIV1(x) (0x0 << (8 + x * 2))
+#define SHIM_CLKCTL_DPCS_DIV2(x) (0x1 << (8 + x * 2))
+#define SHIM_CLKCTL_DPCS_DIV4(x) (0x3 << (8 + x * 2))
+
+/** \brief Tensilica Core Prevent Audio PLL Shutdown */
+#define SHIM_CLKCTL_TCPAPLLS_EN BIT(7)
+#define SHIM_CLKCTL_TCPAPLLS_DIS 0
+
+/** \brief LP domain clock select, 0: PLL, 1: oscillator */
+#define SHIM_CLKCTL_LDCS_XTAL BIT(5)
+#define SHIM_CLKCTL_LDCS_PLL 0
+
+/** \brief HP domain clock select */
+#define SHIM_CLKCTL_HDCS BIT(4)
+#define SHIM_CLKCTL_HDCS_XTAL BIT(4)
+#define SHIM_CLKCTL_HDCS_PLL 0
+
+/** \brief LP domain oscillator clock select select, 0: XTAL, 1: Fast RING */
+#define SHIM_CLKCTL_LDOCS BIT(3)
+
+/** \brief HP domain oscillator clock select select, 0: XTAL, 1: Fast RING */
+#define SHIM_CLKCTL_HDOCS BIT(2)
+
+/** \brief LP memory clock PLL divisor, 0: div by 2, 1: div by 4 */
+#define SHIM_CLKCTL_LPMPCS_DIV4 BIT(1)
+#define SHIM_CLKCTL_LPMPCS_DIV2 0
+
+/** \brief HP memory clock PLL divisor, 0: div by 2, 1: div by 4 */
+#define SHIM_CLKCTL_HPMPCS_DIV4 BIT(0)
+#define SHIM_CLKCTL_HPMPCS_DIV2 0
+
+#define SHIM_PWRCTL 0x90
+#define SHIM_PWRSTS 0x92
+#define SHIM_LPSCTL 0x94
+
+/* HP & LP SRAM Power Gating */
+#define SHIM_HSPGCTL 0x80
+#define SHIM_LSPGCTL 0x84
+#define SHIM_SPSREQ 0xa0
+
+#define SHIM_SPSREQ_RVNNP BIT(0)
+
+/** \brief GPDMA shim registers Control */
+#define SHIM_GPDMA_BASE_OFFSET 0xC00
+#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x80)
+
+/** \brief GPDMA Channel Linear Link Position Control */
+#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + (y) * 0x10)
+#define SHIM_GPDMA_CHLLPC_EN BIT(5)
+#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(4, 0, x)
+
+/** \brief LDO Control */
+#define SHIM_LDOCTL 0xA4
+#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0)
+#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
+#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
+#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
+#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
+#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
+#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
+#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
+
+#define SHIM_HSPGISTS 0xb0
+#define SHIM_LSPGISTS 0xb4
+#define LSPGISTS (SHIM_BASE + SHIM_LSPGISTS)
+
+
+#define SHIM_LPSCTL_FDSPRUN BIT(9)
+#define SHIM_LPSCTL_FDMARUN BIT(8)
+
+#define SHIM_L2_MECS (SHIM_BASE + 0xd0)
+
+#define SHIM_LPGPDMAC(x) (0x1110 + (2 * x))
+#define SHIM_LPGPDMAC_CTLOSEL BIT(15)
+#define SHIM_LPGPDMAC_CHOSEL 0xFF
+
+#define SHIM_DSPIOPO 0x1118
+#define SHIM_DSPIOPO_DMICOSEL BIT(0)
+#define SHIM_DSPIOPO_I2SOSEL (0x3F << 8)
+
+#define SHIM_GENO 0x111C
+#define SHIM_GENO_SHIMOSEL BIT(0)
+#define SHIM_GENO_MDIVOSEL BIT(1)
+#define SHIM_GENO_DIOPTOSEL BIT(2)
+
+#define SHIM_L2_CACHE_CTRL (SHIM_BASE + 0x500)
+#define SHIM_L2_PREF_CFG (SHIM_BASE + 0x508)
+#define SHIM_L2_CACHE_PREF (SHIM_BASE + 0x510)
+
+#define SHIM_SVCFG 0xF4
+#define SHIM_SVCFG_FORCE_L1_EXIT BIT(1)
+
+/* host windows */
+#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0)
+#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4)
+
+#define DMWBA_ENABLE BIT(0)
+#define DMWBA_READONLY BIT(1)
+
+
+#endif /* __PLATFORM_LIB_SHIM_H__ */
diff --git a/soc/xtensa/intel_apl_adsp/linker.ld b/soc/xtensa/intel_adsp/cavs_v15/linker.ld
similarity index 93%
copy from soc/xtensa/intel_apl_adsp/linker.ld
copy to soc/xtensa/intel_adsp/cavs_v15/linker.ld
index 31d64e8..baf3293 100644
--- a/soc/xtensa/intel_apl_adsp/linker.ld
+++ b/soc/xtensa/intel_adsp/cavs_v15/linker.ld
@@ -14,7 +14,8 @@
OUTPUT_ARCH(xtensa)
#include <devicetree.h>
-#include "memory.h"
+#include <xtensa/config/core-isa.h>
+#include <soc/memory.h>
#include <autoconf.h>
#include <linker/sections.h>
@@ -104,6 +105,13 @@
lpram :
org = LPRAM_BASE,
len = LPRAM_SIZE
+
+ static_uuid_entries_seg (!ari) :
+ org = UUID_ENTRY_ELF_BASE,
+ len = UUID_ENTRY_ELF_SIZE
+ static_log_entries_seg (!ari) :
+ org = LOG_ENTRY_ELF_BASE,
+ len = LOG_ENTRY_ELF_SIZE
}
PHDRS
@@ -130,6 +138,9 @@
vector_double_lit_phdr PT_LOAD;
vector_double_text_phdr PT_LOAD;
ram_phdr PT_LOAD;
+
+ static_uuid_entries_phdr PT_NOTE;
+ static_log_entries_phdr PT_NOTE;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@@ -172,17 +183,17 @@
* attributes.
*/
#ifndef CONFIG_SMP
-_memmap_cacheattr_intel_apl_adsp = 0xFF42FFF2;
+_memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;
#else
/*
* FIXME: Make 0xA0000000 - 0xBFFFFFFF to bypass cache under SMP
* since there is no data cache manipulation for spinlock, kernel
* object, scheduler, etc...
*/
-_memmap_cacheattr_intel_apl_adsp = 0xFF22FFF2;
+_memmap_cacheattr_intel_cavs15_adsp = 0xFF22FFF2;
#endif
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_apl_adsp);
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);
SECTIONS
{
@@ -327,6 +338,7 @@
*(.init.literal)
*(.iram0.text)
KEEP(*(.init))
+ KEEP(*(.lps_vector))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
@@ -371,12 +383,19 @@
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >ram :ram_phdr
+ .module_init : ALIGN(4)
+ {
+ _module_init_start = ABSOLUTE(.);
+ *(*.module_init)
+ _module_init_end = ABSOLUTE(.);
+ } >ram :ram_phdr
#include <linker/common-rom.ld>
.fw_ready : ALIGN(4)
{
KEEP(*(".fw_ready"));
+ KEEP (*(.fw_ready_metadata))
} >ram :ram_phdr
.noinit : ALIGN(4)
@@ -503,4 +522,14 @@
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
+
+ .static_uuid_entries (COPY) : ALIGN(1024)
+ {
+ *(*.static_uuids)
+ } > static_uuid_entries_seg :static_uuid_entries_phdr
+
+ .static_log_entries (COPY) : ALIGN(1024)
+ {
+ *(*.static_log*)
+ } > static_log_entries_seg :static_log_entries_phdr
}
diff --git a/soc/xtensa/intel_apl_adsp/Kconfig.defconfig b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series
similarity index 77%
rename from soc/xtensa/intel_apl_adsp/Kconfig.defconfig
rename to soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series
index f439ab6..c4179e4 100644
--- a/soc/xtensa/intel_apl_adsp/Kconfig.defconfig
+++ b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series
@@ -1,23 +1,28 @@
-# Xtensa board configuration
-
-# Copyright (c) 2017 Intel Corporation
+# Copyright (c) 2020 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
-if SOC_INTEL_APL_ADSP
+if SOC_SERIES_INTEL_CAVS_V18
+
+config SOC_SERIES
+ string
+ default "cavs_v18"
config SOC
string
- default "intel_apl_adsp"
+ default "intel_cavs_18"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 400000000 if XTENSA_TIMER
default 19200000 if CAVS_TIMER
+config SYS_CLOCK_TICKS_PER_SEC
+ default 50000
+
config IRQ_OFFLOAD_INTNUM
default 0
-# S1000 does not have MISC0.
-# Since EXCSAVE2 is unused by Zephyr, use it instead.
+# This series does not have MISC0.
+# Since EXCSAVE7 is unused by Zephyr, use it instead.
config XTENSA_KERNEL_CPU_PTR_SR
default "EXCSAVE2"
@@ -51,7 +56,7 @@
default y
config LOG_BACKEND_RB_MEM_BASE
- default 0xBE008000
+ default 0xBE000000
config LOG_BACKEND_RB_MEM_SIZE
default 8192
@@ -78,7 +83,7 @@
config SCHED_IPI_SUPPORTED
default y if IPM_CAVS_IDC
-endif
+endif # SMP
config IPM_INTEL_ADSP
default y
diff --git a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.series b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.series
new file mode 100644
index 0000000..7e81a2f
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.series
@@ -0,0 +1,13 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_INTEL_CAVS_V18
+ bool "Intel CAVS v1.8"
+ select SOC_FAMILY_INTEL_ADSP
+ select XTENSA
+ select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
+ select XTENSA_RESET_VECTOR
+ select XTENSA_USE_CORE_CRT1
+ select ATOMIC_OPERATIONS_BUILTIN
+ help
+ Intel CAVS v1.8
diff --git a/soc/xtensa/intel_adsp/cavs_v18/Kconfig.soc b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.soc
new file mode 100644
index 0000000..71a250b
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v18/Kconfig.soc
@@ -0,0 +1,11 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+ prompt "Intel CAVS SoC Selection"
+
+ config SOC_INTEL_CAVS_V18
+ bool "CAVS v1.8 SoC"
+ depends on SOC_SERIES_INTEL_CAVS_V18
+
+endchoice
diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/_soc_inthandlers.h b/soc/xtensa/intel_adsp/cavs_v18/include/_soc_inthandlers.h
new file mode 100644
index 0000000..37d98da
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v18/include/_soc_inthandlers.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2020 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ *
+ * Functions here are designed to produce efficient code to
+ * search an Xtensa bitmask of interrupts, inspecting only those bits
+ * declared to be associated with a given interrupt level. Each
+ * dispatcher will handle exactly one flagged interrupt, in numerical
+ * order (low bits first) and will return a mask of that bit that can
+ * then be cleared by the calling code. Unrecognized bits for the
+ * level will invoke an error handler.
+ */
+
+#include <xtensa/config/core-isa.h>
+#include <sys/util.h>
+#include <sw_isr_table.h>
+
+#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 4
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 4
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 7
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+
+static inline int _xtensa_handle_one_int1(unsigned int mask)
+{
+ int irq;
+
+ if (mask & 0x3) {
+ if (mask & BIT(0)) {
+ mask = BIT(0);
+ irq = 0;
+ goto handle_irq;
+ }
+ if (mask & BIT(1)) {
+ mask = BIT(1);
+ irq = 1;
+ goto handle_irq;
+ }
+ } else {
+ if (mask & BIT(2)) {
+ mask = BIT(2);
+ irq = 2;
+ goto handle_irq;
+ }
+ if (mask & BIT(3)) {
+ mask = BIT(3);
+ irq = 3;
+ goto handle_irq;
+ }
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int2(unsigned int mask)
+{
+ int irq;
+
+ if (mask & 0x30) {
+ if (mask & BIT(4)) {
+ mask = BIT(4);
+ irq = 4;
+ goto handle_irq;
+ }
+ if (mask & BIT(5)) {
+ mask = BIT(5);
+ irq = 5;
+ goto handle_irq;
+ }
+ } else {
+ if (mask & BIT(6)) {
+ mask = BIT(6);
+ irq = 6;
+ goto handle_irq;
+ }
+ if (mask & BIT(7)) {
+ mask = BIT(7);
+ irq = 7;
+ goto handle_irq;
+ }
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int3(unsigned int mask)
+{
+ int irq;
+
+ if (mask & 0x300) {
+ if (mask & BIT(8)) {
+ mask = BIT(8);
+ irq = 8;
+ goto handle_irq;
+ }
+ if (mask & BIT(9)) {
+ mask = BIT(9);
+ irq = 9;
+ goto handle_irq;
+ }
+ } else {
+ if (mask & BIT(10)) {
+ mask = BIT(10);
+ irq = 10;
+ goto handle_irq;
+ }
+ if (mask & BIT(11)) {
+ mask = BIT(11);
+ irq = 11;
+ goto handle_irq;
+ }
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int4(unsigned int mask)
+{
+ int irq;
+
+ if (mask & BIT(12)) {
+ mask = BIT(12);
+ irq = 12;
+ goto handle_irq;
+ }
+ if (mask & BIT(13)) {
+ mask = BIT(13);
+ irq = 13;
+ goto handle_irq;
+ }
+ if (mask & BIT(14)) {
+ mask = BIT(14);
+ irq = 14;
+ goto handle_irq;
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int5(unsigned int mask)
+{
+ int irq;
+
+ if (mask & 0x18000) {
+ if (mask & BIT(15)) {
+ mask = BIT(15);
+ irq = 15;
+ goto handle_irq;
+ }
+ if (mask & BIT(16)) {
+ mask = BIT(16);
+ irq = 16;
+ goto handle_irq;
+ }
+ } else {
+ if (mask & BIT(17)) {
+ mask = BIT(17);
+ irq = 17;
+ goto handle_irq;
+ }
+ if (mask & BIT(18)) {
+ mask = BIT(18);
+ irq = 18;
+ goto handle_irq;
+ }
+ if (mask & BIT(19)) {
+ mask = BIT(19);
+ irq = 19;
+ goto handle_irq;
+ }
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int7(unsigned int mask)
+{
+ int irq;
+
+ if (mask & BIT(20)) {
+ mask = BIT(20);
+ irq = 20;
+ goto handle_irq;
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int0(unsigned int mask)
+{
+ return 0;
+}
+static inline int _xtensa_handle_one_int6(unsigned int mask)
+{
+ return 0;
+}
diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
new file mode 100644
index 0000000..81a0649
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2019 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_MEMORY_H
+#define __INC_MEMORY_H
+
+#include <cavs/cpu.h>
+
+/* L2 HP SRAM */
+#define HP_RAM_RESERVE_HEADER_SPACE 0x00010000
+
+#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
+#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
+
+#ifdef CONFIG_BOOTLOADER_MCUBOOT
+#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
+#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
+#else
+#define SRAM_BASE (L2_SRAM_BASE)
+#define SRAM_SIZE (L2_SRAM_SIZE)
+#endif
+
+/* The reset vector address in SRAM and its size */
+#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE
+#define MEM_RESET_TEXT_SIZE 0x268
+#define MEM_RESET_LIT_SIZE 0x8
+
+/* This is the base address of all the vectors defined in SRAM */
+#define XCHAL_VECBASE_RESET_PADDR_SRAM \
+ (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE)
+
+#define MEM_VECBASE_LIT_SIZE 0x178
+
+/* The addresses of the vectors in SRAM.
+ * Only the memerror vector continues to point to its ROM address.
+ */
+#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x180)
+
+#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x1C0)
+
+#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x200)
+
+#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x240)
+
+#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x280)
+
+#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x2C0)
+
+#define XCHAL_KERNEL_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x300)
+
+#define XCHAL_USER_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x340)
+
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x3C0)
+
+#define VECTOR_TBL_SIZE 0x0400
+
+/* Vector and literal sizes */
+#define MEM_VECT_LIT_SIZE 0x8
+#define MEM_VECT_TEXT_SIZE 0x38
+#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
+ MEM_VECT_LIT_SIZE)
+
+#define MEM_ERROR_TEXT_SIZE 0x180
+#define MEM_ERROR_LIT_SIZE 0x8
+
+/* text and data share the same L2 HP SRAM.
+ * So, they lie next to each other.
+ */
+#define RAM_BASE \
+ (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
+
+#define RAM_SIZE \
+ (SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
+
+#define LPSRAM_MASK(x) 0x00000003
+
+/* Location for the intList section which is later used to construct the
+ * Interrupt Descriptor Table (IDT). This is a bogus address as this
+ * section will be stripped off in the final image.
+ */
+#define IDT_BASE (RAM_BASE + RAM_SIZE)
+
+/* size of the Interrupt Descriptor Table (IDT) */
+#define IDT_SIZE 0x2000
+
+/* low power ram where DMA buffers are typically placed */
+#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
+#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
+
+/* bootloader */
+
+#define HP_SRAM_BASE 0xbe000000
+#define HP_SRAM_SIZE (3008 * 1024)
+#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
+
+/* boot loader in IMR */
+#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000
+#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120
+
+#define IMR_BOOT_LDR_LIT_BASE \
+ (IMR_BOOT_LDR_TEXT_ENTRY_BASE + IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
+#define IMR_BOOT_LDR_LIT_SIZE 0x100
+
+#define IMR_BOOT_LDR_TEXT_BASE \
+ (IMR_BOOT_LDR_LIT_BASE + IMR_BOOT_LDR_LIT_SIZE)
+#define IMR_BOOT_LDR_TEXT_SIZE 0x1c00
+
+#define IMR_BOOT_LDR_DATA_BASE 0xb0039000
+#define IMR_BOOT_LDR_DATA_SIZE 0x1000
+
+#define IMR_BOOT_LDR_BSS_BASE 0xb0100000
+#define IMR_BOOT_LDR_BSS_SIZE 0x1000
+
+#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \
+ BOOT_LDR_STACK_SIZE)
+#define BOOT_LDR_STACK_SIZE (4 * 0x1000)
+
+/* Manifest base address in IMR - used by boot loader copy procedure. */
+#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000
+
+/* Manifest size (seems unused). */
+#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000
+
+
+#define UUID_ENTRY_ELF_BASE 0x1FFFA000
+#define UUID_ENTRY_ELF_SIZE 0x6000
+
+#define LOG_ENTRY_ELF_BASE 0x20000000
+#define LOG_ENTRY_ELF_SIZE 0x2000000
+
+
+#define SRAM_ALIAS_BASE 0x9E000000
+#define SRAM_ALIAS_MASK 0xFF000000
+#define SRAM_ALIAS_OFFSET 0x20000000
+
+
+#define uncache_to_cache(address) \
+ ((__typeof__((address)))((uint32_t)((address)) + SRAM_ALIAS_OFFSET))
+#define cache_to_uncache(address) \
+ ((__typeof__((address)))((uint32_t)((address)) - SRAM_ALIAS_OFFSET))
+#define is_uncached(address) \
+ (((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_ALIAS_BASE)
+
+/* shim */
+#define SHIM_BASE 0x00071F00
+#define SHIM_SIZE 0x00000100
+
+/* IRQ controller */
+#define IRQ_BASE 0x00078800
+#define IRQ_SIZE 0x00000200
+
+/* IPC to the host */
+#define IPC_HOST_BASE 0x00071E00
+#define IPC_HOST_SIZE 0x00000020
+
+/* intra DSP IPC */
+#define IPC_DSP_SIZE 0x00000080
+#define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE)
+
+/* SRAM window for HOST */
+#define HOST_WIN_SIZE 0x00000008
+#define HOST_WIN_BASE(x) (0x00071A00 + x * HOST_WIN_SIZE)
+
+/* HP SRAM windows */
+
+/* window 3 */
+#define SRAM_TRACE_BASE 0xbe000000
+#define SRAM_TRACE_SIZE 0x2000
+
+#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE
+#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
+
+/* window 2 */
+#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE)
+#define SRAM_DEBUG_SIZE 0x800
+
+#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
+#define SRAM_EXCEPT_SIZE 0x800
+
+#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
+#define SRAM_STREAM_SIZE 0x1000
+
+/* window 1 */
+#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
+#define SRAM_INBOX_SIZE 0x2000
+
+/* window 0 */
+#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
+#define SRAM_SW_REG_SIZE 0x1000
+
+#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
+#define SRAM_OUTBOX_SIZE 0x1000
+
+#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE
+#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE)
+
+
+#define SOF_TEXT_START 0xbe010400
+
+#define SOF_TEXT_BASE SOF_TEXT_START
+
+/* SRAM window 0 FW "registers" */
+#define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14
+#define SRAM_REG_FW_END \
+ (SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4)
+
+/* Host page size */
+#define HOST_PAGE_SIZE 4096
+
+#define SRAM_BANK_SIZE (64 * 1024)
+
+#endif /* __INC_MEMORY_H */
diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/platform.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/platform.h
new file mode 100644
index 0000000..f5a796b
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/platform.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ * Keyon Jie <yang.jie@linux.intel.com>
+ * Xiuli Pan <xiuli.pan@linux.intel.com>
+ */
+
+#ifndef __PLATFORM_PLATFORM_H__
+#define __PLATFORM_PLATFORM_H__
+
+#define PLATFORM_PRIMARY_CORE_ID 0
+
+#define MAX_CORE_COUNT 4
+
+#define PLATFORM_HPSRAM_EBB_COUNT 47
+
+#define EBB_SEGMENT_SIZE 32
+
+#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
+#error "Invalid core count - exceeding core limit"
+#endif
+
+#endif /* __PLATFORM_PLATFORM_H__ */
diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h
new file mode 100644
index 0000000..2102883
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: Apache-2.0
+
+ *
+ * Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ * Keyon Jie <yang.jie@linux.intel.com>
+ * Rander Wang <rander.wang@intel.com>
+ */
+
+#ifndef __PLATFORM_LIB_SHIM_H__
+#define __PLATFORM_LIB_SHIM_H__
+
+#include <sys/util.h>
+#include <soc/memory.h>
+
+#ifndef ASSEMBLY
+#include <stdint.h>
+#endif
+
+#if !defined(__ASSEMBLER__) && !defined(LINKER)
+#include <sys/sys_io.h>
+#include <arch/common/sys_io.h>
+#endif
+
+#ifndef BIT
+#define BIT(b) (1 << (b))
+#endif
+
+/* DSP IPC for Host Registers */
+#define IPC_DIPCTDR 0x00
+#define IPC_DIPCTDA 0x04
+#define IPC_DIPCTDD 0x08
+#define IPC_DIPCIDR 0x10
+#define IPC_DIPCIDA 0x14
+#define IPC_DIPCIDD 0x18
+#define IPC_DIPCCTL 0x28
+
+#define IPC_DSP_OFFSET 0x10
+
+/* DSP IPC for intra DSP communication */
+#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET)
+#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET)
+#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET)
+#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET)
+#define IPC_IDCCTL 0x50
+
+/* IDCTFC */
+#define IPC_IDCTFC_BUSY BIT(31)
+#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF
+
+/* IDCTEFC */
+#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF
+
+/* IDCITC */
+#define IPC_IDCITC_BUSY BIT(31)
+#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF
+
+/* IDCIETC */
+#define IPC_IDCIETC_DONE BIT(30)
+#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF
+
+/* IDCCTL */
+#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x))
+#define IPC_IDCCTL_IDCTBIE(x) BIT(x)
+
+#define IRQ_CPU_OFFSET 0x40
+
+#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL2MD_ALL 0x03F181F0
+
+#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL3MD_ALL 0x807F81FF
+
+#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL4MD_ALL 0x807F81FF
+
+#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF
+
+#define REG_IRQ_IL2RSD 0x100
+#define REG_IRQ_IL3RSD 0x104
+#define REG_IRQ_IL4RSD 0x108
+#define REG_IRQ_IL5RSD 0x10c
+
+#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16)
+#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24)
+
+/* DSP Shim Registers */
+#define SHIM_DSPWC 0x20 /* DSP Wall Clock */
+#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */
+#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */
+#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */
+
+#define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */
+#define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */
+#define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */
+#define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */
+
+/** \brief Clock control */
+#define SHIM_CLKCTL 0x78
+
+/** \brief Request HP RING Oscillator Clock */
+#define SHIM_CLKCTL_RHROSCC BIT(31)
+
+/** \brief Request XTAL Oscillator Clock */
+#define SHIM_CLKCTL_RXOSCC BIT(30)
+
+/** \brief Request LP RING Oscillator Clock */
+#define SHIM_CLKCTL_RLROSCC BIT(29)
+
+/** \brief Tensilica Core Prevent Local Clock Gating */
+#define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x))
+#define SHIM_CLKCTL_TCPLCG_DIS(x) 0
+#define SHIM_CLKCTL_TCPLCG_DIS_ALL (SHIM_CLKCTL_TCPLCG_DIS(0) | \
+ SHIM_CLKCTL_TCPLCG_DIS(1) | \
+ SHIM_CLKCTL_TCPLCG_DIS(2) | \
+ SHIM_CLKCTL_TCPLCG_DIS(3))
+
+/** \brief Core clock PLL divisor */
+#define SHIM_CLKCTL_DPCS_MASK(x) BIT(2)
+
+/** \brief DMIC Force Dynamic Clock Gating */
+#define SHIM_CLKCTL_DMICFDCGB BIT(30)
+
+/** \brief Oscillator Clock Select*/
+#define SHIM_CLKCTL_OCS_HP_RING BIT(2)
+#define SHIM_CLKCTL_OCS_LP_RING 0
+
+/** \brief LP Memory Clock Select */
+#define SHIM_CLKCTL_LMCS_DIV2 0
+#define SHIM_CLKCTL_LMCS_DIV4 BIT(1)
+
+/** \brief HP Memory Clock Select */
+#define SHIM_CLKCTL_HMCS_DIV2 0
+#define SHIM_CLKCTL_HMCS_DIV4 BIT(0)
+
+/* Core clock PLL divisor */
+#define SHIM_CLKCTL_DPCS_MASK(x) BIT(2)
+
+/* Prevent Audio PLL Shutdown */
+#define SHIM_CLKCTL_TCPAPLLS BIT(7)
+
+/* 0--from PLL, 1--from oscillator */
+#define SHIM_CLKCTL_HDCS BIT(4)
+
+/* Oscillator select */
+#define SHIM_CLKCTL_HDOCS BIT(2)
+
+/* HP memory clock PLL divisor */
+#define SHIM_CLKCTL_HPMPCS BIT(0)
+
+/** \brief Mask for requesting clock
+ */
+#define SHIM_CLKCTL_OSC_REQUEST_MASK \
+ (SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_RXOSCC | \
+ SHIM_CLKCTL_RLROSCC)
+
+/** \brief Mask for setting previously requested clock
+ */
+#define SHIM_CLKCTL_OSC_SOURCE_MASK \
+ (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \
+ SHIM_CLKCTL_HMCS_DIV4)
+
+/** \brief Clock status */
+#define SHIM_CLKSTS 0x7C
+
+/** \brief HP RING Oscillator Clock Status */
+#define SHIM_CLKSTS_HROSCCS BIT(31)
+
+/** \brief XTAL Oscillator Clock Status */
+#define SHIM_CLKSTS_XOSCCS BIT(30)
+
+/** \brief LP RING Oscillator Clock Status */
+#define SHIM_CLKSTS_LROSCCS BIT(29)
+
+#define SHIM_PWRCTL 0x90
+#define SHIM_PWRCTL_TCPDSPPG(x) BIT(x)
+#define SHIM_PWRCTL_TCPCTLPG BIT(4)
+
+#define SHIM_PWRSTS 0x92
+
+#define SHIM_LPSCTL 0x94
+#define SHIM_LPSCTL_BID BIT(7)
+#define SHIM_LPSCTL_FDSPRUN BIT(9)
+#define SHIM_LPSCTL_BATTR_0 BIT(12)
+
+/** \brief GPDMA shim registers Control */
+#define SHIM_GPDMA_BASE_OFFSET 0x6500
+#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
+
+/** \brief GPDMA Clock Control */
+#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4)
+/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
+#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
+
+/** \brief GPDMA Channel Linear Link Position Control */
+#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10)
+#define SHIM_GPDMA_CHLLPC_EN BIT(7)
+#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
+
+#define L2LMCAP 0x71D00
+#define L2MPAT 0x71D04
+
+#define HSPGCTL0 0x71D10
+#define HSRMCTL0 0x71D14
+#define HSPGISTS0 0x71D18
+
+#define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x))
+#define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x))
+
+#define HSPGCTL1 0x71D20
+#define HSRMCTL1 0x71D24
+#define HSPGISTS1 0x71D28
+
+#define LSPGCTL 0x71D50
+#define LSRMCTL 0x71D54
+#define LSPGISTS 0x71D58
+
+#define SHIM_LSPGCTL 0x50
+#define SHIM_LSPGISTS 0x58
+
+
+#define SHIM_L2_MECS (SHIM_BASE + 0xd0)
+
+/** \brief LDO Control */
+#define SHIM_LDOCTL 0xA4
+#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0)
+#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
+#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
+#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
+#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
+#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
+#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
+#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
+
+#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
+#define LPGPDMA_CTLOSEL_FLAG BIT(15)
+#define LPGPDMA_CHOSEL_FLAG 0xFF
+
+#define DSP_INIT_IOPO 0x71A68
+#define IOPO_DMIC_FLAG BIT(0)
+#define IOPO_I2S_FLAG (7 << 8)
+
+#define DSP_INIT_GENO 0x71A6C
+#define GENO_MDIVOSEL BIT(1)
+#define GENO_DIOPTOSEL BIT(2)
+
+#define DSP_INIT_ALHO 0x71A70
+#define ALHO_ASO_FLAG BIT(0)
+#define ALHO_CSO_FLAG BIT(1)
+#define ALHO_CFO_FLAG BIT(2)
+
+#define SHIM_SVCFG 0xF4
+#define SHIM_SVCFG_FORCE_L1_EXIT BIT(1)
+
+/* host windows */
+#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0)
+#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4)
+
+#define DMWBA_ENABLE BIT(0)
+#define DMWBA_READONLY BIT(1)
+
+/* DMIC power ON bit */
+#define DMICLCTL_SPA ((uint32_t) BIT(0))
+
+/* DMIC disable clock gating */
+#define DMIC_DCGD ((uint32_t) BIT(30))
+
+#endif /* __PLATFORM_LIB_SHIM_H__ */
diff --git a/soc/xtensa/intel_apl_adsp/linker.ld b/soc/xtensa/intel_adsp/cavs_v18/linker.ld
similarity index 93%
copy from soc/xtensa/intel_apl_adsp/linker.ld
copy to soc/xtensa/intel_adsp/cavs_v18/linker.ld
index 31d64e8..7ab8a51 100644
--- a/soc/xtensa/intel_apl_adsp/linker.ld
+++ b/soc/xtensa/intel_adsp/cavs_v18/linker.ld
@@ -14,7 +14,8 @@
OUTPUT_ARCH(xtensa)
#include <devicetree.h>
-#include "memory.h"
+#include <xtensa/config/core-isa.h>
+#include <soc/memory.h>
#include <autoconf.h>
#include <linker/sections.h>
@@ -104,6 +105,13 @@
lpram :
org = LPRAM_BASE,
len = LPRAM_SIZE
+
+ static_uuid_entries_seg (!ari) :
+ org = UUID_ENTRY_ELF_BASE,
+ len = UUID_ENTRY_ELF_SIZE
+ static_log_entries_seg (!ari) :
+ org = LOG_ENTRY_ELF_BASE,
+ len = LOG_ENTRY_ELF_SIZE
}
PHDRS
@@ -130,6 +138,9 @@
vector_double_lit_phdr PT_LOAD;
vector_double_text_phdr PT_LOAD;
ram_phdr PT_LOAD;
+
+ static_uuid_entries_phdr PT_NOTE;
+ static_log_entries_phdr PT_NOTE;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@@ -172,17 +183,17 @@
* attributes.
*/
#ifndef CONFIG_SMP
-_memmap_cacheattr_intel_apl_adsp = 0xFF42FFF2;
+_memmap_cacheattr_intel_cavs18_adsp = 0xFF42FFF2;
#else
/*
* FIXME: Make 0xA0000000 - 0xBFFFFFFF to bypass cache under SMP
* since there is no data cache manipulation for spinlock, kernel
* object, scheduler, etc...
*/
-_memmap_cacheattr_intel_apl_adsp = 0xFF22FFF2;
+_memmap_cacheattr_intel_cavs18_adsp = 0xFF22FFF2;
#endif
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_apl_adsp);
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs18_adsp);
SECTIONS
{
@@ -327,6 +338,7 @@
*(.init.literal)
*(.iram0.text)
KEEP(*(.init))
+ KEEP(*(.lps_vector))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
@@ -371,12 +383,19 @@
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >ram :ram_phdr
+ .module_init : ALIGN(4)
+ {
+ _module_init_start = ABSOLUTE(.);
+ *(*.module_init)
+ _module_init_end = ABSOLUTE(.);
+ } >ram :ram_phdr
#include <linker/common-rom.ld>
.fw_ready : ALIGN(4)
{
KEEP(*(".fw_ready"));
+ KEEP (*(.fw_ready_metadata))
} >ram :ram_phdr
.noinit : ALIGN(4)
@@ -503,4 +522,14 @@
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
+
+ .static_uuid_entries (COPY) : ALIGN(1024)
+ {
+ *(*.static_uuids)
+ } > static_uuid_entries_seg :static_uuid_entries_phdr
+
+ .static_log_entries (COPY) : ALIGN(1024)
+ {
+ *(*.static_log*)
+ } > static_log_entries_seg :static_log_entries_phdr
}
diff --git a/soc/xtensa/intel_apl_adsp/Kconfig.defconfig b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series
similarity index 68%
copy from soc/xtensa/intel_apl_adsp/Kconfig.defconfig
copy to soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series
index f439ab6..4e51a07 100644
--- a/soc/xtensa/intel_apl_adsp/Kconfig.defconfig
+++ b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series
@@ -1,23 +1,28 @@
-# Xtensa board configuration
-
-# Copyright (c) 2017 Intel Corporation
+# Copyright (c) 2020 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
-if SOC_INTEL_APL_ADSP
+if SOC_SERIES_INTEL_CAVS_V20
+
+config SOC_SERIES
+ string
+ default "cavs_v20"
config SOC
string
- default "intel_apl_adsp"
+ default "intel_cavs_20"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 400000000 if XTENSA_TIMER
default 19200000 if CAVS_TIMER
+config SYS_CLOCK_TICKS_PER_SEC
+ default 50000
+
config IRQ_OFFLOAD_INTNUM
default 0
-# S1000 does not have MISC0.
-# Since EXCSAVE2 is unused by Zephyr, use it instead.
+# This series does not have MISC0.
+# Since EXCSAVE7 is unused by Zephyr, use it instead.
config XTENSA_KERNEL_CPU_PTR_SR
default "EXCSAVE2"
@@ -43,15 +48,14 @@
if LOG
-# When console is enabled printk should go through it
config LOG_PRINTK
- default y if !CONSOLE
+ default y
config LOG_BACKEND_RB
default y
config LOG_BACKEND_RB_MEM_BASE
- default 0xBE008000
+ default 0xBE000000
config LOG_BACKEND_RB_MEM_SIZE
default 8192
@@ -78,15 +82,6 @@
config SCHED_IPI_SUPPORTED
default y if IPM_CAVS_IDC
-endif
+endif # SMP
-config IPM_INTEL_ADSP
- default y
- depends on IPM
-
-config IPM_CONSOLE
- default y
- depends on CONSOLE
- depends on IPM
-
-endif
+endif # SOC_SERIES_INTEL_CAVS_V20
diff --git a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.series b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.series
new file mode 100644
index 0000000..e50d6f2
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.series
@@ -0,0 +1,13 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_INTEL_CAVS_V20
+ bool "Intel CAVS v2.0"
+ select SOC_FAMILY_INTEL_ADSP
+ select XTENSA
+ select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
+ select XTENSA_RESET_VECTOR
+ select XTENSA_USE_CORE_CRT1
+ select ATOMIC_OPERATIONS_BUILTIN
+ help
+ Intel CAVS v2.0
diff --git a/soc/xtensa/intel_adsp/cavs_v20/Kconfig.soc b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.soc
new file mode 100644
index 0000000..0b44f61
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v20/Kconfig.soc
@@ -0,0 +1,11 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+ prompt "Intel CAVS SoC Selection"
+
+ config SOC_INTEL_CAVS_V20
+ bool "CAVS v2.0 SoC"
+ depends on SOC_SERIES_INTEL_CAVS_V20
+
+endchoice
diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/_soc_inthandlers.h b/soc/xtensa/intel_adsp/cavs_v20/include/_soc_inthandlers.h
new file mode 100644
index 0000000..37d98da
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v20/include/_soc_inthandlers.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2020 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ *
+ * Functions here are designed to produce efficient code to
+ * search an Xtensa bitmask of interrupts, inspecting only those bits
+ * declared to be associated with a given interrupt level. Each
+ * dispatcher will handle exactly one flagged interrupt, in numerical
+ * order (low bits first) and will return a mask of that bit that can
+ * then be cleared by the calling code. Unrecognized bits for the
+ * level will invoke an error handler.
+ */
+
+#include <xtensa/config/core-isa.h>
+#include <sys/util.h>
+#include <sw_isr_table.h>
+
+#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 4
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 4
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 7
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+
+static inline int _xtensa_handle_one_int1(unsigned int mask)
+{
+ int irq;
+
+ if (mask & 0x3) {
+ if (mask & BIT(0)) {
+ mask = BIT(0);
+ irq = 0;
+ goto handle_irq;
+ }
+ if (mask & BIT(1)) {
+ mask = BIT(1);
+ irq = 1;
+ goto handle_irq;
+ }
+ } else {
+ if (mask & BIT(2)) {
+ mask = BIT(2);
+ irq = 2;
+ goto handle_irq;
+ }
+ if (mask & BIT(3)) {
+ mask = BIT(3);
+ irq = 3;
+ goto handle_irq;
+ }
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int2(unsigned int mask)
+{
+ int irq;
+
+ if (mask & 0x30) {
+ if (mask & BIT(4)) {
+ mask = BIT(4);
+ irq = 4;
+ goto handle_irq;
+ }
+ if (mask & BIT(5)) {
+ mask = BIT(5);
+ irq = 5;
+ goto handle_irq;
+ }
+ } else {
+ if (mask & BIT(6)) {
+ mask = BIT(6);
+ irq = 6;
+ goto handle_irq;
+ }
+ if (mask & BIT(7)) {
+ mask = BIT(7);
+ irq = 7;
+ goto handle_irq;
+ }
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int3(unsigned int mask)
+{
+ int irq;
+
+ if (mask & 0x300) {
+ if (mask & BIT(8)) {
+ mask = BIT(8);
+ irq = 8;
+ goto handle_irq;
+ }
+ if (mask & BIT(9)) {
+ mask = BIT(9);
+ irq = 9;
+ goto handle_irq;
+ }
+ } else {
+ if (mask & BIT(10)) {
+ mask = BIT(10);
+ irq = 10;
+ goto handle_irq;
+ }
+ if (mask & BIT(11)) {
+ mask = BIT(11);
+ irq = 11;
+ goto handle_irq;
+ }
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int4(unsigned int mask)
+{
+ int irq;
+
+ if (mask & BIT(12)) {
+ mask = BIT(12);
+ irq = 12;
+ goto handle_irq;
+ }
+ if (mask & BIT(13)) {
+ mask = BIT(13);
+ irq = 13;
+ goto handle_irq;
+ }
+ if (mask & BIT(14)) {
+ mask = BIT(14);
+ irq = 14;
+ goto handle_irq;
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int5(unsigned int mask)
+{
+ int irq;
+
+ if (mask & 0x18000) {
+ if (mask & BIT(15)) {
+ mask = BIT(15);
+ irq = 15;
+ goto handle_irq;
+ }
+ if (mask & BIT(16)) {
+ mask = BIT(16);
+ irq = 16;
+ goto handle_irq;
+ }
+ } else {
+ if (mask & BIT(17)) {
+ mask = BIT(17);
+ irq = 17;
+ goto handle_irq;
+ }
+ if (mask & BIT(18)) {
+ mask = BIT(18);
+ irq = 18;
+ goto handle_irq;
+ }
+ if (mask & BIT(19)) {
+ mask = BIT(19);
+ irq = 19;
+ goto handle_irq;
+ }
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int7(unsigned int mask)
+{
+ int irq;
+
+ if (mask & BIT(20)) {
+ mask = BIT(20);
+ irq = 20;
+ goto handle_irq;
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int0(unsigned int mask)
+{
+ return 0;
+}
+static inline int _xtensa_handle_one_int6(unsigned int mask)
+{
+ return 0;
+}
diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
new file mode 100644
index 0000000..ddb3564
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2019 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_MEMORY_H
+#define __INC_MEMORY_H
+
+#include <cavs/cpu.h>
+
+/* L2 HP SRAM */
+#define HP_RAM_RESERVE_HEADER_SPACE 0x00010000
+
+#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
+#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
+
+#ifdef CONFIG_BOOTLOADER_MCUBOOT
+#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
+#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
+#else
+#define SRAM_BASE (L2_SRAM_BASE)
+#define SRAM_SIZE (L2_SRAM_SIZE)
+#endif
+
+/* The reset vector address in SRAM and its size */
+#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE
+#define MEM_RESET_TEXT_SIZE 0x268
+#define MEM_RESET_LIT_SIZE 0x8
+
+/* This is the base address of all the vectors defined in SRAM */
+#define XCHAL_VECBASE_RESET_PADDR_SRAM \
+ (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE)
+
+#define MEM_VECBASE_LIT_SIZE 0x178
+
+/* The addresses of the vectors in SRAM.
+ * Only the memerror vector continues to point to its ROM address.
+ */
+#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x180)
+
+#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x1C0)
+
+#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x200)
+
+#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x240)
+
+#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x280)
+
+#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x2C0)
+
+#define XCHAL_KERNEL_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x300)
+
+#define XCHAL_USER_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x340)
+
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x3C0)
+
+#define VECTOR_TBL_SIZE 0x0400
+
+/* Vector and literal sizes */
+#define MEM_VECT_LIT_SIZE 0x8
+#define MEM_VECT_TEXT_SIZE 0x38
+#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
+ MEM_VECT_LIT_SIZE)
+
+#define MEM_ERROR_TEXT_SIZE 0x180
+#define MEM_ERROR_LIT_SIZE 0x8
+
+/* text and data share the same L2 HP SRAM.
+ * So, they lie next to each other.
+ */
+#define RAM_BASE \
+ (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
+
+#define RAM_SIZE \
+ (SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
+
+#define LPSRAM_MASK(x) 0x00000003
+
+/* Location for the intList section which is later used to construct the
+ * Interrupt Descriptor Table (IDT). This is a bogus address as this
+ * section will be stripped off in the final image.
+ */
+#define IDT_BASE (RAM_BASE + RAM_SIZE)
+
+/* size of the Interrupt Descriptor Table (IDT) */
+#define IDT_SIZE 0x2000
+
+/* low power ram where DMA buffers are typically placed */
+#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
+#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
+
+/* bootloader */
+
+#define HP_SRAM_BASE 0xbe000000
+#define HP_SRAM_SIZE (3008 * 1024)
+#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
+
+/* boot loader in IMR */
+#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000
+#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120
+
+#define IMR_BOOT_LDR_LIT_BASE \
+ (IMR_BOOT_LDR_TEXT_ENTRY_BASE + IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
+#define IMR_BOOT_LDR_LIT_SIZE 0x100
+
+#define IMR_BOOT_LDR_TEXT_BASE \
+ (IMR_BOOT_LDR_LIT_BASE + IMR_BOOT_LDR_LIT_SIZE)
+#define IMR_BOOT_LDR_TEXT_SIZE 0x1c00
+
+#define IMR_BOOT_LDR_DATA_BASE 0xb0039000
+#define IMR_BOOT_LDR_DATA_SIZE 0x1000
+
+#define IMR_BOOT_LDR_BSS_BASE 0xb0100000
+#define IMR_BOOT_LDR_BSS_SIZE 0x1000
+
+#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \
+ BOOT_LDR_STACK_SIZE)
+#define BOOT_LDR_STACK_SIZE (4 * 0x1000)
+
+/* Manifest base address in IMR - used by boot loader copy procedure. */
+#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000
+
+/* Manifest size (seems unused). */
+#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000
+
+
+#define UUID_ENTRY_ELF_BASE 0x1FFFA000
+#define UUID_ENTRY_ELF_SIZE 0x6000
+
+#define LOG_ENTRY_ELF_BASE 0x20000000
+#define LOG_ENTRY_ELF_SIZE 0x2000000
+
+
+#define SRAM_ALIAS_BASE 0x9E000000
+#define SRAM_ALIAS_MASK 0xFF000000
+#define SRAM_ALIAS_OFFSET 0x20000000
+
+
+#define uncache_to_cache(address) \
+ ((__typeof__((address)))((uint32_t)((address)) + SRAM_ALIAS_OFFSET))
+#define cache_to_uncache(address) \
+ ((__typeof__((address)))((uint32_t)((address)) - SRAM_ALIAS_OFFSET))
+#define is_uncached(address) \
+ (((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_ALIAS_BASE)
+
+/* shim */
+#define SHIM_BASE 0x00071F00
+#define SHIM_SIZE 0x00000100
+
+/* IRQ controller */
+#define IRQ_BASE 0x00078800
+#define IRQ_SIZE 0x00000200
+
+/* IPC to the host */
+#define IPC_HOST_BASE 0x00071E00
+#define IPC_HOST_SIZE 0x00000020
+
+/* intra DSP IPC */
+#define IPC_DSP_SIZE 0x00000080
+#define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE)
+
+/* SRAM window for HOST */
+#define HOST_WIN_SIZE 0x00000008
+#define HOST_WIN_BASE(x) (0x00071A00 + x * HOST_WIN_SIZE)
+
+/* HP SRAM windows */
+
+/* window 3 */
+#define SRAM_TRACE_BASE 0xbe000000
+#define SRAM_TRACE_SIZE 0x2000
+
+#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE
+#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
+
+/* window 2 */
+#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE)
+#define SRAM_DEBUG_SIZE 0x800
+
+#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
+#define SRAM_EXCEPT_SIZE 0x800
+
+#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
+#define SRAM_STREAM_SIZE 0x1000
+
+/* window 1 */
+#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
+#define SRAM_INBOX_SIZE 0x2000
+
+/* window 0 */
+#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
+#define SRAM_SW_REG_SIZE 0x1000
+
+#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
+#define SRAM_OUTBOX_SIZE 0x1000
+
+#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE
+#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE)
+
+
+#define SOF_TEXT_START 0xbe010400
+
+#define SOF_TEXT_BASE SOF_TEXT_START
+
+/* SRAM window 0 FW "registers" */
+#define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14
+#define SRAM_REG_FW_END \
+ (SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4)
+
+/* Host page size */
+#define HOST_PAGE_SIZE 4096
+
+#define SRAM_BANK_SIZE (64 * 1024)
+
+#endif /* __INC_MEMORY_H */
diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/platform.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/platform.h
new file mode 100644
index 0000000..9db1670
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/platform.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ * Keyon Jie <yang.jie@linux.intel.com>
+ * Rander Wang <rander.wang@intel.com>
+ * Xiuli Pan <xiuli.pan@linux.intel.com>
+ */
+
+#ifndef __PLATFORM_PLATFORM_H__
+#define __PLATFORM_PLATFORM_H__
+
+#define PLATFORM_RESET_MHE_AT_BOOT 1
+
+#define PLATFORM_MEM_INIT_AT_BOOT 1
+
+#define PLATFORM_PRIMARY_CORE_ID 0
+
+#define MAX_CORE_COUNT 4
+
+#define PLATFORM_HPSRAM_EBB_COUNT 47
+
+#define EBB_SEGMENT_SIZE 32
+
+#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
+#error "Invalid core count - exceeding core limit"
+#endif
+
+#endif /* __PLATFORM_PLATFORM_H__ */
diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h
new file mode 100644
index 0000000..97aeef6
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h
@@ -0,0 +1,283 @@
+/* SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ * Keyon Jie <yang.jie@linux.intel.com>
+ * Rander Wang <rander.wang@intel.com>
+ */
+
+#ifndef __PLATFORM_LIB_SHIM_H__
+#define __PLATFORM_LIB_SHIM_H__
+
+#include <sys/util.h>
+#include <soc/memory.h>
+
+#ifndef ASSEMBLY
+#include <stdint.h>
+#endif
+
+#if !defined(__ASSEMBLER__) && !defined(LINKER)
+#include <sys/sys_io.h>
+#include <arch/common/sys_io.h>
+#endif
+
+#ifndef BIT
+#define BIT(b) (1 << (b))
+#endif
+
+/* DSP IPC for Host Registers */
+#define IPC_DIPCTDR 0x00
+#define IPC_DIPCTDA 0x04
+#define IPC_DIPCTDD 0x08
+#define IPC_DIPCIDR 0x10
+#define IPC_DIPCIDA 0x14
+#define IPC_DIPCIDD 0x18
+#define IPC_DIPCCTL 0x28
+
+#define IPC_DSP_OFFSET 0x10
+
+/* DSP IPC for intra DSP communication */
+#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET)
+#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET)
+#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET)
+#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET)
+#define IPC_IDCCTL 0x50
+
+/* IDCTFC */
+#define IPC_IDCTFC_BUSY BIT(31)
+#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF
+
+/* IDCTEFC */
+#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF
+
+/* IDCITC */
+#define IPC_IDCITC_BUSY BIT(31)
+#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF
+
+/* IDCIETC */
+#define IPC_IDCIETC_DONE BIT(30)
+#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF
+
+/* IDCCTL */
+#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x))
+#define IPC_IDCCTL_IDCTBIE(x) BIT(x)
+
+#define IRQ_CPU_OFFSET 0x40
+
+#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL2MD_ALL 0x03F181F0
+
+#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL3MD_ALL 0x807F81FF
+
+#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL4MD_ALL 0x807F81FF
+
+#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF
+
+#define REG_IRQ_IL2RSD 0x100
+#define REG_IRQ_IL3RSD 0x104
+#define REG_IRQ_IL4RSD 0x108
+#define REG_IRQ_IL5RSD 0x10c
+
+#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16)
+#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24)
+
+/* DSP Shim Registers */
+#define SHIM_DSPWC 0x20 /* DSP Wall Clock */
+#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */
+#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */
+#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */
+
+#define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */
+#define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */
+#define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */
+#define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */
+
+/** \brief Clock control */
+#define SHIM_CLKCTL 0x78
+
+/** \brief Request HP RING Oscillator Clock */
+#define SHIM_CLKCTL_RHROSCC BIT(31)
+
+/** \brief Request XTAL Oscillator Clock */
+#define SHIM_CLKCTL_RXOSCC BIT(30)
+
+/** \brief Request LP RING Oscillator Clock */
+#define SHIM_CLKCTL_RLROSCC BIT(29)
+
+/** \brief Tensilica Core Prevent Local Clock Gating */
+#define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x))
+#define SHIM_CLKCTL_TCPLCG_DIS(x) 0
+#define SHIM_CLKCTL_TCPLCG_DIS_ALL (SHIM_CLKCTL_TCPLCG_DIS(0) | \
+ SHIM_CLKCTL_TCPLCG_DIS(1) | \
+ SHIM_CLKCTL_TCPLCG_DIS(2) | \
+ SHIM_CLKCTL_TCPLCG_DIS(3))
+
+/** \brief Oscillator Clock Select*/
+#define SHIM_CLKCTL_OCS_HP_RING BIT(2)
+#define SHIM_CLKCTL_OCS_LP_RING 0
+
+/** \brief LP Memory Clock Select */
+#define SHIM_CLKCTL_LMCS_DIV2 0
+#define SHIM_CLKCTL_LMCS_DIV4 BIT(1)
+
+/** \brief HP Memory Clock Select */
+#define SHIM_CLKCTL_HMCS_DIV2 0
+#define SHIM_CLKCTL_HMCS_DIV4 BIT(0)
+
+/* Core clock PLL divisor */
+#define SHIM_CLKCTL_DPCS_MASK(x) BIT(2)
+
+/* Prevent Audio PLL Shutdown */
+#define SHIM_CLKCTL_TCPAPLLS BIT(7)
+
+/* 0--from PLL, 1--from oscillator */
+#define SHIM_CLKCTL_HDCS BIT(4)
+
+/* Oscillator select */
+#define SHIM_CLKCTL_HDOCS BIT(2)
+
+/* HP memory clock PLL divisor */
+#define SHIM_CLKCTL_HPMPCS BIT(0)
+
+/** \brief Mask for requesting clock
+ */
+#define SHIM_CLKCTL_OSC_REQUEST_MASK \
+ (SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_RXOSCC | \
+ SHIM_CLKCTL_RLROSCC)
+
+/** \brief Mask for setting previously requested clock
+ */
+#define SHIM_CLKCTL_OSC_SOURCE_MASK \
+ (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \
+ SHIM_CLKCTL_HMCS_DIV4)
+
+/** \brief Clock status */
+#define SHIM_CLKSTS 0x7C
+
+/** \brief HP RING Oscillator Clock Status */
+#define SHIM_CLKSTS_HROSCCS BIT(31)
+
+/** \brief XTAL Oscillator Clock Status */
+#define SHIM_CLKSTS_XOSCCS BIT(30)
+
+/** \brief LP RING Oscillator Clock Status */
+#define SHIM_CLKSTS_LROSCCS BIT(29)
+
+#define SHIM_PWRCTL 0x90
+#define SHIM_PWRCTL_TCPDSPPG(x) BIT(x)
+#define SHIM_PWRCTL_TCPCTLPG BIT(4)
+
+#define SHIM_PWRSTS 0x92
+
+#define SHIM_LPSCTL 0x94
+#define SHIM_LPSCTL_BID BIT(7)
+#define SHIM_LPSCTL_FDSPRUN BIT(9)
+#define SHIM_LPSCTL_BATTR_0 BIT(12)
+
+/** \brief GPDMA shim registers Control */
+#define SHIM_GPDMA_BASE_OFFSET 0x6500
+#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
+
+/** \brief GPDMA Clock Control */
+#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4)
+/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
+#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
+
+/** \brief GPDMA Channel Linear Link Position Control */
+#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10)
+#define SHIM_GPDMA_CHLLPC_EN BIT(7)
+#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
+
+#define L2LMCAP 0x71D00
+#define L2MPAT 0x71D04
+
+#define HSPGCTL0 0x71D10
+#define HSRMCTL0 0x71D14
+#define HSPGISTS0 0x71D18
+
+#define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x))
+#define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x))
+
+#define HSPGCTL1 0x71D20
+#define HSRMCTL1 0x71D24
+#define HSPGISTS1 0x71D28
+
+#define LSPGCTL 0x71D50
+#define LSRMCTL 0x71D54
+#define LSPGISTS 0x71D58
+
+#define SHIM_LSPGCTL 0x50
+#define SHIM_LSPGISTS 0x58
+
+
+#define SHIM_L2_MECS (SHIM_BASE + 0xd0)
+
+/** \brief LDO Control */
+#define SHIM_LDOCTL 0xA4
+#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0)
+#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
+#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
+#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
+#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
+#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
+#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
+#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
+
+#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
+#define LPGPDMA_CTLOSEL_FLAG BIT(15)
+#define LPGPDMA_CHOSEL_FLAG 0xFF
+
+#define DSP_INIT_IOPO 0x71A68
+#define IOPO_DMIC_FLAG BIT(0)
+#define IOPO_I2S_FLAG GENMASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8)
+
+#define DSP_INIT_GENO 0x71A6C
+#define GENO_MDIVOSEL BIT(1)
+#define GENO_DIOPTOSEL BIT(2)
+
+#define DSP_INIT_ALHO 0x71A70
+#define ALHO_ASO_FLAG BIT(0)
+#define ALHO_CSO_FLAG BIT(1)
+#define ALHO_CFO_FLAG BIT(2)
+
+#define SHIM_SVCFG 0xF4
+#define SHIM_SVCFG_FORCE_L1_EXIT BIT(1)
+
+/* host windows */
+#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0)
+#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4)
+
+#define DMWBA_ENABLE BIT(0)
+#define DMWBA_READONLY BIT(1)
+
+/* DMIC power ON bit */
+#define DMICLCTL_SPA ((uint32_t) BIT(0))
+
+/* DMIC disable clock gating */
+#define DMIC_DCGD ((uint32_t) BIT(30))
+
+#endif /* __PLATFORM_LIB_SHIM_H__ */
diff --git a/soc/xtensa/intel_apl_adsp/linker.ld b/soc/xtensa/intel_adsp/cavs_v20/linker.ld
similarity index 93%
rename from soc/xtensa/intel_apl_adsp/linker.ld
rename to soc/xtensa/intel_adsp/cavs_v20/linker.ld
index 31d64e8..c24adfe 100644
--- a/soc/xtensa/intel_apl_adsp/linker.ld
+++ b/soc/xtensa/intel_adsp/cavs_v20/linker.ld
@@ -14,7 +14,8 @@
OUTPUT_ARCH(xtensa)
#include <devicetree.h>
-#include "memory.h"
+#include <xtensa/config/core-isa.h>
+#include <soc/memory.h>
#include <autoconf.h>
#include <linker/sections.h>
@@ -104,6 +105,13 @@
lpram :
org = LPRAM_BASE,
len = LPRAM_SIZE
+
+ static_uuid_entries_seg (!ari) :
+ org = UUID_ENTRY_ELF_BASE,
+ len = UUID_ENTRY_ELF_SIZE
+ static_log_entries_seg (!ari) :
+ org = LOG_ENTRY_ELF_BASE,
+ len = LOG_ENTRY_ELF_SIZE
}
PHDRS
@@ -130,6 +138,9 @@
vector_double_lit_phdr PT_LOAD;
vector_double_text_phdr PT_LOAD;
ram_phdr PT_LOAD;
+
+ static_uuid_entries_phdr PT_NOTE;
+ static_log_entries_phdr PT_NOTE;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@@ -172,17 +183,17 @@
* attributes.
*/
#ifndef CONFIG_SMP
-_memmap_cacheattr_intel_apl_adsp = 0xFF42FFF2;
+_memmap_cacheattr_intel_cavs20_adsp = 0xFF42FFF2;
#else
/*
* FIXME: Make 0xA0000000 - 0xBFFFFFFF to bypass cache under SMP
* since there is no data cache manipulation for spinlock, kernel
* object, scheduler, etc...
*/
-_memmap_cacheattr_intel_apl_adsp = 0xFF22FFF2;
+_memmap_cacheattr_intel_cavs20_adsp = 0xFF22FFF2;
#endif
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_apl_adsp);
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs20_adsp);
SECTIONS
{
@@ -327,6 +338,7 @@
*(.init.literal)
*(.iram0.text)
KEEP(*(.init))
+ KEEP(*(.lps_vector))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
@@ -371,12 +383,19 @@
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >ram :ram_phdr
+ .module_init : ALIGN(4)
+ {
+ _module_init_start = ABSOLUTE(.);
+ *(*.module_init)
+ _module_init_end = ABSOLUTE(.);
+ } >ram :ram_phdr
#include <linker/common-rom.ld>
.fw_ready : ALIGN(4)
{
KEEP(*(".fw_ready"));
+ KEEP (*(.fw_ready_metadata))
} >ram :ram_phdr
.noinit : ALIGN(4)
@@ -503,4 +522,14 @@
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
+
+ .static_uuid_entries (COPY) : ALIGN(1024)
+ {
+ *(*.static_uuids)
+ } > static_uuid_entries_seg :static_uuid_entries_phdr
+
+ .static_log_entries (COPY) : ALIGN(1024)
+ {
+ *(*.static_log*)
+ } > static_log_entries_seg :static_log_entries_phdr
}
diff --git a/soc/xtensa/intel_apl_adsp/Kconfig.defconfig b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series
similarity index 68%
copy from soc/xtensa/intel_apl_adsp/Kconfig.defconfig
copy to soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series
index f439ab6..3e8a83d 100644
--- a/soc/xtensa/intel_apl_adsp/Kconfig.defconfig
+++ b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series
@@ -1,23 +1,28 @@
-# Xtensa board configuration
-
-# Copyright (c) 2017 Intel Corporation
+# Copyright (c) 2020 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
-if SOC_INTEL_APL_ADSP
+if SOC_SERIES_INTEL_CAVS_V25
+
+config SOC_SERIES
+ string
+ default "cavs_v25"
config SOC
string
- default "intel_apl_adsp"
+ default "intel_cavs_25"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 400000000 if XTENSA_TIMER
default 19200000 if CAVS_TIMER
+config SYS_CLOCK_TICKS_PER_SEC
+ default 50000
+
config IRQ_OFFLOAD_INTNUM
default 0
-# S1000 does not have MISC0.
-# Since EXCSAVE2 is unused by Zephyr, use it instead.
+# This series does not have MISC0.
+# Since EXCSAVE7 is unused by Zephyr, use it instead.
config XTENSA_KERNEL_CPU_PTR_SR
default "EXCSAVE2"
@@ -43,15 +48,14 @@
if LOG
-# When console is enabled printk should go through it
config LOG_PRINTK
- default y if !CONSOLE
+ default y
config LOG_BACKEND_RB
default y
config LOG_BACKEND_RB_MEM_BASE
- default 0xBE008000
+ default 0xBE000000
config LOG_BACKEND_RB_MEM_SIZE
default 8192
@@ -78,15 +82,6 @@
config SCHED_IPI_SUPPORTED
default y if IPM_CAVS_IDC
-endif
+endif # SMP
-config IPM_INTEL_ADSP
- default y
- depends on IPM
-
-config IPM_CONSOLE
- default y
- depends on CONSOLE
- depends on IPM
-
-endif
+endif # SOC_SERIES_INTEL_CAVS_V25
diff --git a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.series b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.series
new file mode 100644
index 0000000..554c487
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.series
@@ -0,0 +1,13 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_INTEL_CAVS_V25
+ bool "Intel CAVS v2.5"
+ select SOC_FAMILY_INTEL_ADSP
+ select XTENSA
+ select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
+ select XTENSA_RESET_VECTOR
+ select XTENSA_USE_CORE_CRT1
+ select ATOMIC_OPERATIONS_BUILTIN
+ help
+ Intel CAVS v2.5
diff --git a/soc/xtensa/intel_adsp/cavs_v25/Kconfig.soc b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.soc
new file mode 100644
index 0000000..04d9ca8
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v25/Kconfig.soc
@@ -0,0 +1,11 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+ prompt "Intel CAVS SoC Selection"
+
+ config SOC_INTEL_CAVS_V25
+ bool "CAVS v2.5 SoC"
+ depends on SOC_SERIES_INTEL_CAVS_V25
+
+endchoice
diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/_soc_inthandlers.h b/soc/xtensa/intel_adsp/cavs_v25/include/_soc_inthandlers.h
new file mode 100644
index 0000000..37d98da
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v25/include/_soc_inthandlers.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2020 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ *
+ * Functions here are designed to produce efficient code to
+ * search an Xtensa bitmask of interrupts, inspecting only those bits
+ * declared to be associated with a given interrupt level. Each
+ * dispatcher will handle exactly one flagged interrupt, in numerical
+ * order (low bits first) and will return a mask of that bit that can
+ * then be cleared by the calling code. Unrecognized bits for the
+ * level will invoke an error handler.
+ */
+
+#include <xtensa/config/core-isa.h>
+#include <sys/util.h>
+#include <sw_isr_table.h>
+
+#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 4
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 4
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 7
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+
+static inline int _xtensa_handle_one_int1(unsigned int mask)
+{
+ int irq;
+
+ if (mask & 0x3) {
+ if (mask & BIT(0)) {
+ mask = BIT(0);
+ irq = 0;
+ goto handle_irq;
+ }
+ if (mask & BIT(1)) {
+ mask = BIT(1);
+ irq = 1;
+ goto handle_irq;
+ }
+ } else {
+ if (mask & BIT(2)) {
+ mask = BIT(2);
+ irq = 2;
+ goto handle_irq;
+ }
+ if (mask & BIT(3)) {
+ mask = BIT(3);
+ irq = 3;
+ goto handle_irq;
+ }
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int2(unsigned int mask)
+{
+ int irq;
+
+ if (mask & 0x30) {
+ if (mask & BIT(4)) {
+ mask = BIT(4);
+ irq = 4;
+ goto handle_irq;
+ }
+ if (mask & BIT(5)) {
+ mask = BIT(5);
+ irq = 5;
+ goto handle_irq;
+ }
+ } else {
+ if (mask & BIT(6)) {
+ mask = BIT(6);
+ irq = 6;
+ goto handle_irq;
+ }
+ if (mask & BIT(7)) {
+ mask = BIT(7);
+ irq = 7;
+ goto handle_irq;
+ }
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int3(unsigned int mask)
+{
+ int irq;
+
+ if (mask & 0x300) {
+ if (mask & BIT(8)) {
+ mask = BIT(8);
+ irq = 8;
+ goto handle_irq;
+ }
+ if (mask & BIT(9)) {
+ mask = BIT(9);
+ irq = 9;
+ goto handle_irq;
+ }
+ } else {
+ if (mask & BIT(10)) {
+ mask = BIT(10);
+ irq = 10;
+ goto handle_irq;
+ }
+ if (mask & BIT(11)) {
+ mask = BIT(11);
+ irq = 11;
+ goto handle_irq;
+ }
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int4(unsigned int mask)
+{
+ int irq;
+
+ if (mask & BIT(12)) {
+ mask = BIT(12);
+ irq = 12;
+ goto handle_irq;
+ }
+ if (mask & BIT(13)) {
+ mask = BIT(13);
+ irq = 13;
+ goto handle_irq;
+ }
+ if (mask & BIT(14)) {
+ mask = BIT(14);
+ irq = 14;
+ goto handle_irq;
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int5(unsigned int mask)
+{
+ int irq;
+
+ if (mask & 0x18000) {
+ if (mask & BIT(15)) {
+ mask = BIT(15);
+ irq = 15;
+ goto handle_irq;
+ }
+ if (mask & BIT(16)) {
+ mask = BIT(16);
+ irq = 16;
+ goto handle_irq;
+ }
+ } else {
+ if (mask & BIT(17)) {
+ mask = BIT(17);
+ irq = 17;
+ goto handle_irq;
+ }
+ if (mask & BIT(18)) {
+ mask = BIT(18);
+ irq = 18;
+ goto handle_irq;
+ }
+ if (mask & BIT(19)) {
+ mask = BIT(19);
+ irq = 19;
+ goto handle_irq;
+ }
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int7(unsigned int mask)
+{
+ int irq;
+
+ if (mask & BIT(20)) {
+ mask = BIT(20);
+ irq = 20;
+ goto handle_irq;
+ }
+ return 0;
+handle_irq:
+ _sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+ return mask;
+}
+
+static inline int _xtensa_handle_one_int0(unsigned int mask)
+{
+ return 0;
+}
+static inline int _xtensa_handle_one_int6(unsigned int mask)
+{
+ return 0;
+}
diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
new file mode 100644
index 0000000..b5005b9
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
@@ -0,0 +1,242 @@
+s/*
+ * Copyright (c) 2019 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_MEMORY_H
+#define __INC_MEMORY_H
+
+#include <cavs/cpu.h>
+
+/* L2 HP SRAM */
+#define HP_RAM_RESERVE_HEADER_SPACE 0x00010000
+
+#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
+#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
+
+#ifdef CONFIG_BOOTLOADER_MCUBOOT
+#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
+#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
+#else
+#define SRAM_BASE (L2_SRAM_BASE)
+#define SRAM_SIZE (L2_SRAM_SIZE)
+#endif
+
+/* The reset vector address in SRAM and its size */
+#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE
+#define MEM_RESET_TEXT_SIZE 0x268
+#define MEM_RESET_LIT_SIZE 0x8
+
+/* This is the base address of all the vectors defined in SRAM */
+#define XCHAL_VECBASE_RESET_PADDR_SRAM \
+ (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE)
+
+#define MEM_VECBASE_LIT_SIZE 0x178
+
+/* The addresses of the vectors in SRAM.
+ * Only the memerror vector continues to point to its ROM address.
+ */
+#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x180)
+
+#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x1C0)
+
+#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x200)
+
+#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x240)
+
+#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x280)
+
+#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x2C0)
+
+#define XCHAL_KERNEL_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x300)
+
+#define XCHAL_USER_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x340)
+
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM \
+ (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x3C0)
+
+#define VECTOR_TBL_SIZE 0x0400
+
+/* Vector and literal sizes */
+#define MEM_VECT_LIT_SIZE 0x8
+#define MEM_VECT_TEXT_SIZE 0x38
+#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
+ MEM_VECT_LIT_SIZE)
+
+#define MEM_ERROR_TEXT_SIZE 0x180
+#define MEM_ERROR_LIT_SIZE 0x8
+
+/* text and data share the same L2 HP SRAM.
+ * So, they lie next to each other.
+ */
+#define RAM_BASE \
+ (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
+
+#define RAM_SIZE \
+ (SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
+
+#define LPSRAM_MASK(x) 0x00000003
+
+/* Location for the intList section which is later used to construct the
+ * Interrupt Descriptor Table (IDT). This is a bogus address as this
+ * section will be stripped off in the final image.
+ */
+#define IDT_BASE (RAM_BASE + RAM_SIZE)
+
+/* size of the Interrupt Descriptor Table (IDT) */
+#define IDT_SIZE 0x2000
+
+/* low power ram where DMA buffers are typically placed */
+#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
+#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
+
+/* bootloader */
+
+#define HP_SRAM_BASE 0xbe000000
+#define HP_SRAM_SIZE (3008 * 1024)
+#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
+
+/* boot loader in IMR */
+#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000
+#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120
+
+#define IMR_BOOT_LDR_LIT_BASE \
+ (IMR_BOOT_LDR_TEXT_ENTRY_BASE + IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
+#define IMR_BOOT_LDR_LIT_SIZE 0x100
+
+#define IMR_BOOT_LDR_TEXT_BASE \
+ (IMR_BOOT_LDR_LIT_BASE + IMR_BOOT_LDR_LIT_SIZE)
+#define IMR_BOOT_LDR_TEXT_SIZE 0x1c00
+
+#define IMR_BOOT_LDR_DATA_BASE 0xb0039000
+#define IMR_BOOT_LDR_DATA_SIZE 0x1000
+
+#define IMR_BOOT_LDR_BSS_BASE 0xb0100000
+#define IMR_BOOT_LDR_BSS_SIZE 0x1000
+
+#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \
+ BOOT_LDR_STACK_SIZE)
+#define BOOT_LDR_STACK_SIZE (4 * 0x1000)
+
+/* Manifest base address in IMR - used by boot loader copy procedure. */
+#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000
+
+/* Manifest size (seems unused). */
+#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000
+
+
+#define UUID_ENTRY_ELF_BASE 0x1FFFA000
+#define UUID_ENTRY_ELF_SIZE 0x6000
+
+#define LOG_ENTRY_ELF_BASE 0x20000000
+#define LOG_ENTRY_ELF_SIZE 0x2000000
+
+
+#define SRAM_ALIAS_BASE 0x9E000000
+#define SRAM_ALIAS_MASK 0xFF000000
+#define SRAM_ALIAS_OFFSET 0x20000000
+
+
+#define uncache_to_cache(address) \
+ ((__typeof__((address)))((uint32_t)((address)) + SRAM_ALIAS_OFFSET))
+#define cache_to_uncache(address) \
+ ((__typeof__((address)))((uint32_t)((address)) - SRAM_ALIAS_OFFSET))
+#define is_uncached(address) \
+ (((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_ALIAS_BASE)
+
+/* shim */
+#define SHIM_BASE 0x00071F00
+#define SHIM_SIZE 0x00000100
+
+/* IRQ controller */
+#define IRQ_BASE 0x00078800
+#define IRQ_SIZE 0x00000200
+
+/* IPC to the host */
+#define IPC_HOST_BASE 0x00071E00
+#define IPC_HOST_SIZE 0x00000020
+
+/* intra DSP IPC */
+#define IPC_DSP_SIZE 0x00000080
+#define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE)
+
+/* SRAM window for HOST */
+#define HOST_WIN_SIZE 0x00000008
+#define HOST_WIN_BASE(x) (0x00071A00 + x * HOST_WIN_SIZE)
+
+/* HP SRAM windows */
+
+/* window 3 */
+#define SRAM_TRACE_BASE 0xbe000000
+#define SRAM_TRACE_SIZE 0x2000
+
+#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE
+#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
+
+/* window 2 */
+#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE)
+#define SRAM_DEBUG_SIZE 0x800
+
+#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
+#define SRAM_EXCEPT_SIZE 0x800
+
+#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
+#define SRAM_STREAM_SIZE 0x1000
+
+/* window 1 */
+#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
+#define SRAM_INBOX_SIZE 0x2000
+
+/* window 0 */
+#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
+#define SRAM_SW_REG_SIZE 0x1000
+
+#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
+#define SRAM_OUTBOX_SIZE 0x1000
+
+#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE
+#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE)
+
+
+#define SOF_TEXT_START 0xbe010400
+
+#define SOF_TEXT_BASE SOF_TEXT_START
+
+/* SRAM window 0 FW "registers" */
+#define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14
+#define SRAM_REG_FW_END \
+ (SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4)
+
+/* Host page size */
+#define HOST_PAGE_SIZE 4096
+
+#define SRAM_BANK_SIZE (64 * 1024)
+
+/* LP SRAM */
+#define LP_SRAM_BASE 0xBE800000
+
+#define LP_SRAM_SIZE (0x10000 * 2)
+
+/* alternate reset vector */
+#define LP_SRAM_ALT_RESET_VEC_BASE LP_SRAM_BASE
+#define LP_SRAM_ALT_RESET_VEC_SIZE 0x180
+
+#define LP_SRAM_ALT_RESET_INT_VEC_BASE (LP_SRAM_ALT_RESET_VEC_BASE + \
+ LP_SRAM_ALT_RESET_VEC_SIZE)
+#define LP_SRAM_ALT_RESET_INT_VEC_SIZE 0x10
+
+#define LP_SRAM_CODE_BASE (LP_SRAM_ALT_RESET_INT_VEC_BASE + \
+ LP_SRAM_ALT_RESET_INT_VEC_SIZE)
+#define LP_SRAM_CODE_SIZE 0x220
+
+#define LP_SRAM_START (LP_SRAM_CODE_BASE + LP_SRAM_CODE_SIZE)
+
+#endif /* __INC_MEMORY_H */
diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h
new file mode 100644
index 0000000..9db1670
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ * Keyon Jie <yang.jie@linux.intel.com>
+ * Rander Wang <rander.wang@intel.com>
+ * Xiuli Pan <xiuli.pan@linux.intel.com>
+ */
+
+#ifndef __PLATFORM_PLATFORM_H__
+#define __PLATFORM_PLATFORM_H__
+
+#define PLATFORM_RESET_MHE_AT_BOOT 1
+
+#define PLATFORM_MEM_INIT_AT_BOOT 1
+
+#define PLATFORM_PRIMARY_CORE_ID 0
+
+#define MAX_CORE_COUNT 4
+
+#define PLATFORM_HPSRAM_EBB_COUNT 47
+
+#define EBB_SEGMENT_SIZE 32
+
+#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
+#error "Invalid core count - exceeding core limit"
+#endif
+
+#endif /* __PLATFORM_PLATFORM_H__ */
diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h
new file mode 100644
index 0000000..7356d62
--- /dev/null
+++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h
@@ -0,0 +1,292 @@
+/* SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ * Keyon Jie <yang.jie@linux.intel.com>
+ * Rander Wang <rander.wang@intel.com>
+ */
+
+#ifndef __PLATFORM_LIB_SHIM_H__
+#define __PLATFORM_LIB_SHIM_H__
+
+#include <sys/util.h>
+#include <soc/memory.h>
+
+#ifndef ASSEMBLY
+#include <stdint.h>
+#endif
+
+#if !defined(__ASSEMBLER__) && !defined(LINKER)
+#include <sys/sys_io.h>
+#include <arch/common/sys_io.h>
+#endif
+
+#ifndef BIT
+#define BIT(b) (1 << (b))
+#endif
+
+/* DSP IPC for Host Registers */
+#define IPC_DIPCTDR 0x00
+#define IPC_DIPCTDA 0x04
+#define IPC_DIPCTDD 0x08
+#define IPC_DIPCIDR 0x10
+#define IPC_DIPCIDA 0x14
+#define IPC_DIPCIDD 0x18
+#define IPC_DIPCCTL 0x28
+
+#define IPC_DSP_OFFSET 0x10
+
+/* DSP IPC for intra DSP communication */
+#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET)
+#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET)
+#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET)
+#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET)
+#define IPC_IDCCTL 0x50
+
+/* IDCTFC */
+#define IPC_IDCTFC_BUSY BIT(31)
+#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF
+
+/* IDCTEFC */
+#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF
+
+/* IDCITC */
+#define IPC_IDCITC_BUSY BIT(31)
+#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF
+
+/* IDCIETC */
+#define IPC_IDCIETC_DONE BIT(30)
+#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF
+
+/* IDCCTL */
+#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x))
+#define IPC_IDCCTL_IDCTBIE(x) BIT(x)
+
+#define IRQ_CPU_OFFSET 0x40
+
+#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL2MD_ALL 0x03F181F0
+
+#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL3MD_ALL 0x807F81FF
+
+#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL4MD_ALL 0x807F81FF
+
+#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF
+
+#define REG_IRQ_IL2RSD 0x100
+#define REG_IRQ_IL3RSD 0x104
+#define REG_IRQ_IL4RSD 0x108
+#define REG_IRQ_IL5RSD 0x10c
+
+#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16)
+#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24)
+
+/* DSP Shim Registers */
+#define SHIM_DSPWC 0x20 /* DSP Wall Clock */
+#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */
+#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */
+#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */
+
+#define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */
+#define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */
+#define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */
+#define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */
+
+/** \brief Clock control */
+#define SHIM_CLKCTL 0x78
+
+/** \brief Request HP RING Oscillator Clock */
+#define SHIM_CLKCTL_RHROSCC BIT(31)
+
+/** \brief Request XTAL Oscillator Clock */
+#define SHIM_CLKCTL_RXOSCC BIT(30)
+
+/** \brief Request LP RING Oscillator Clock */
+#define SHIM_CLKCTL_RLROSCC BIT(29)
+
+/** \brief Tensilica Core Prevent Local Clock Gating */
+#define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x))
+#define SHIM_CLKCTL_TCPLCG_DIS(x) 0
+#define SHIM_CLKCTL_TCPLCG_DIS_ALL (SHIM_CLKCTL_TCPLCG_DIS(0) | \
+ SHIM_CLKCTL_TCPLCG_DIS(1) | \
+ SHIM_CLKCTL_TCPLCG_DIS(2) | \
+ SHIM_CLKCTL_TCPLCG_DIS(3))
+
+/** \brief Oscillator Clock Select*/
+#define SHIM_CLKCTL_OCS_HP_RING BIT(2)
+#define SHIM_CLKCTL_OCS_LP_RING 0
+
+/** \brief LP Memory Clock Select */
+#define SHIM_CLKCTL_LMCS_DIV2 0
+#define SHIM_CLKCTL_LMCS_DIV4 BIT(1)
+
+/** \brief HP Memory Clock Select */
+#define SHIM_CLKCTL_HMCS_DIV2 0
+#define SHIM_CLKCTL_HMCS_DIV4 BIT(0)
+
+/* Core clock PLL divisor */
+#define SHIM_CLKCTL_DPCS_MASK(x) BIT(2)
+
+/* Prevent Audio PLL Shutdown */
+#define SHIM_CLKCTL_TCPAPLLS BIT(7)
+
+/* 0--from PLL, 1--from oscillator */
+#define SHIM_CLKCTL_HDCS BIT(4)
+
+/* Oscillator select */
+#define SHIM_CLKCTL_HDOCS BIT(2)
+
+/* HP memory clock PLL divisor */
+#define SHIM_CLKCTL_HPMPCS BIT(0)
+
+/** \brief Mask for requesting clock
+ */
+#define SHIM_CLKCTL_OSC_REQUEST_MASK \
+ (SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_RXOSCC | \
+ SHIM_CLKCTL_RLROSCC)
+
+/** \brief Mask for setting previously requested clock
+ */
+#define SHIM_CLKCTL_OSC_SOURCE_MASK \
+ (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \
+ SHIM_CLKCTL_HMCS_DIV4)
+
+/** \brief Clock status */
+#define SHIM_CLKSTS 0x7C
+
+/** \brief HP RING Oscillator Clock Status */
+#define SHIM_CLKSTS_HROSCCS BIT(31)
+
+/** \brief XTAL Oscillator Clock Status */
+#define SHIM_CLKSTS_XOSCCS BIT(30)
+
+/** \brief LP RING Oscillator Clock Status */
+#define SHIM_CLKSTS_LROSCCS BIT(29)
+
+#define SHIM_PWRCTL 0x90
+#define SHIM_PWRCTL_TCPDSPPG(x) BIT(x)
+#define SHIM_PWRCTL_TCPCTLPG BIT(4)
+
+#define SHIM_PWRSTS 0x92
+
+#define SHIM_LPSCTL 0x94
+#define SHIM_LPSCTL_BID BIT(7)
+#define SHIM_LPSCTL_FDSPRUN BIT(9)
+#define SHIM_LPSCTL_BATTR_0 BIT(12)
+
+/** \brief GPDMA shim registers Control */
+#define SHIM_GPDMA_BASE_OFFSET 0x6500
+#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
+
+/** \brief GPDMA Clock Control */
+#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4)
+/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
+#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
+
+/** \brief GPDMA Channel Linear Link Position Control */
+#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10)
+#define SHIM_GPDMA_CHLLPC_EN BIT(7)
+#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
+
+/* I2S SHIM Registers */
+#define I2SLCTL 0x71C04
+
+/* SPA register should be set for each I2S port and DSP should
+ * wait for CPA to be set
+ */
+#define I2SLCTL_SPA(x) BIT(0 + x)
+#define I2SLCTL_CPA(x) BIT(8 + x)
+
+#define L2LMCAP 0x71D00
+#define L2MPAT 0x71D04
+
+#define HSPGCTL0 0x71D10
+#define HSRMCTL0 0x71D14
+#define HSPGISTS0 0x71D18
+
+#define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x))
+#define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x))
+
+#define HSPGCTL1 0x71D20
+#define HSRMCTL1 0x71D24
+#define HSPGISTS1 0x71D28
+
+#define LSPGCTL 0x71D50
+#define LSRMCTL 0x71D54
+#define LSPGISTS 0x71D58
+
+#define SHIM_LSPGCTL 0x50
+#define SHIM_LSPGISTS 0x58
+
+
+#define SHIM_L2_MECS (SHIM_BASE + 0xd0)
+
+/** \brief LDO Control */
+#define SHIM_LDOCTL 0xA4
+#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0)
+#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
+#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
+#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
+#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
+#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
+#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
+#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
+
+#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
+#define LPGPDMA_CTLOSEL_FLAG BIT(15)
+#define LPGPDMA_CHOSEL_FLAG 0xFF
+
+#define DSP_INIT_IOPO 0x71A68
+#define IOPO_DMIC_FLAG BIT(0)
+#define IOPO_I2S_FLAG GENMASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8)
+
+#define DSP_INIT_GENO 0x71A6C
+#define GENO_MDIVOSEL BIT(1)
+#define GENO_DIOPTOSEL BIT(2)
+
+#define DSP_INIT_ALHO 0x71A70
+#define ALHO_ASO_FLAG BIT(0)
+#define ALHO_CSO_FLAG BIT(1)
+#define ALHO_CFO_FLAG BIT(2)
+
+#define SHIM_SVCFG 0xF4
+#define SHIM_SVCFG_FORCE_L1_EXIT BIT(1)
+
+/* host windows */
+#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0)
+#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4)
+
+#define DMWBA_ENABLE BIT(0)
+#define DMWBA_READONLY BIT(1)
+
+/* DMIC power ON bit */
+#define DMICLCTL_SPA ((uint32_t) BIT(0))
+
+/* DMIC disable clock gating */
+#define DMIC_DCGD ((uint32_t) BIT(30))
+
+#endif /* __PLATFORM_LIB_SHIM_H__ */
diff --git a/soc/xtensa/intel_apl_adsp/linker.ld b/soc/xtensa/intel_adsp/cavs_v25/linker.ld
similarity index 82%
copy from soc/xtensa/intel_apl_adsp/linker.ld
copy to soc/xtensa/intel_adsp/cavs_v25/linker.ld
index 31d64e8..4fca115 100644
--- a/soc/xtensa/intel_apl_adsp/linker.ld
+++ b/soc/xtensa/intel_adsp/cavs_v25/linker.ld
@@ -14,7 +14,8 @@
OUTPUT_ARCH(xtensa)
#include <devicetree.h>
-#include "memory.h"
+#include <xtensa/config/core-isa.h>
+#include <soc/memory.h>
#include <autoconf.h>
#include <linker/sections.h>
@@ -104,6 +105,26 @@
lpram :
org = LPRAM_BASE,
len = LPRAM_SIZE
+
+ static_uuid_entries_seg (!ari) :
+ org = UUID_ENTRY_ELF_BASE,
+ len = UUID_ENTRY_ELF_SIZE
+ static_log_entries_seg (!ari) :
+ org = LOG_ENTRY_ELF_BASE,
+ len = LOG_ENTRY_ELF_SIZE
+
+ lpsram_alt_reset_vec_seg :
+ org = LP_SRAM_ALT_RESET_VEC_BASE,
+ len = LP_SRAM_ALT_RESET_VEC_SIZE
+ lpsram_alt_reset_int_vec_seg :
+ org = LP_SRAM_ALT_RESET_INT_VEC_BASE,
+ len = LP_SRAM_ALT_RESET_INT_VEC_SIZE
+ lpsram_code_seg :
+ org = LP_SRAM_CODE_BASE,
+ len = LP_SRAM_CODE_SIZE
+ lpsram_mem :
+ org = LP_SRAM_START,
+ len = LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE)
}
PHDRS
@@ -130,11 +151,21 @@
vector_double_lit_phdr PT_LOAD;
vector_double_text_phdr PT_LOAD;
ram_phdr PT_LOAD;
+
+ static_uuid_entries_phdr PT_NOTE;
+ static_log_entries_phdr PT_NOTE;
+
+ lpsram_mem_phdr PT_LOAD;
+ sram_alt_fw_reset_vec_phdr PT_LOAD;
+ sram_alt_fw_reset_vec_int_phdr PT_LOAD;
+ lpsram_code_phdr PT_LOAD;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
ENTRY(CONFIG_KERNEL_ENTRY)
+EXTERN(_LpsramHeader)
+EXTERN(_AltResetVector)
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x44024000;
@@ -172,17 +203,17 @@
* attributes.
*/
#ifndef CONFIG_SMP
-_memmap_cacheattr_intel_apl_adsp = 0xFF42FFF2;
+_memmap_cacheattr_intel_cavs25_adsp = 0xFF42FFF2;
#else
/*
* FIXME: Make 0xA0000000 - 0xBFFFFFFF to bypass cache under SMP
* since there is no data cache manipulation for spinlock, kernel
* object, scheduler, etc...
*/
-_memmap_cacheattr_intel_apl_adsp = 0xFF22FFF2;
+_memmap_cacheattr_intel_cavs25_adsp = 0xFF22FFF2;
#endif
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_apl_adsp);
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp);
SECTIONS
{
@@ -327,6 +358,7 @@
*(.init.literal)
*(.iram0.text)
KEEP(*(.init))
+ KEEP(*(.lps_vector))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
@@ -336,6 +368,30 @@
. = ALIGN(4096);
} >ram :ram_phdr
+ .AlternateResetVector.text : ALIGN(64)
+ {
+ _alternate_reset_vector_start = ABSOLUTE(.);
+ KEEP (*(*.AlternateResetVector.text))
+ . = ALIGN(16);
+ _alternate_reset_vector_start_end = ABSOLUTE(.);
+ } >lpsram_alt_reset_vec_seg AT> ram : sram_alt_fw_reset_vec_phdr
+
+ .AlternateResetL2IntVector.text : ALIGN(16)
+ {
+ _alternate_reset_l2_int_vector_start = ABSOLUTE(.);
+ KEEP (*(*.AlternateResetL2IntVector.text))
+ . = ALIGN(16);
+ _alternate_reset_l2_int_vector_end = ABSOLUTE(.);
+ } >lpsram_alt_reset_int_vec_seg AT> ram : sram_alt_fw_reset_vec_int_phdr
+
+ .LpsramCode.text : ALIGN(16)
+ {
+ _lpsram_code_start = ABSOLUTE(.);
+ KEEP (*(*.LpsramCode.text))
+ . = ALIGN(16);
+ _lpsram_code_end = ABSOLUTE(.);
+ } >lpsram_code_seg AT> ram : lpsram_code_phdr
+
.rodata : ALIGN(4096)
{
_rodata_start = ABSOLUTE(.);
@@ -371,12 +427,19 @@
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >ram :ram_phdr
+ .module_init : ALIGN(4)
+ {
+ _module_init_start = ABSOLUTE(.);
+ *(*.module_init)
+ _module_init_end = ABSOLUTE(.);
+ } >ram :ram_phdr
#include <linker/common-rom.ld>
.fw_ready : ALIGN(4)
{
KEEP(*(".fw_ready"));
+ KEEP (*(.fw_ready_metadata))
} >ram :ram_phdr
.noinit : ALIGN(4)
@@ -415,6 +478,30 @@
} >ram :ram_phdr
#include <linker/common-ram.ld>
+ .AltBootManifest : ALIGN(8)
+ {
+ /* Single entry of strorage manifest
+ * consist of 3 items. Entries array
+ * is preceded by a single dword with
+ * entries count. */
+ _loader_storage_manifest_start = ABSOLUTE(.);
+ /* Number of entries*/
+ LONG(3);
+ /* Entry 1 */
+ LONG(LOADADDR(.AlternateResetVector.text));
+ LONG(ADDR(.AlternateResetVector.text));
+ LONG(SIZEOF(.AlternateResetVector.text));
+ /* Entry 2 */
+ LONG(LOADADDR(.AlternateResetL2IntVector.text));
+ LONG(ADDR(.AlternateResetL2IntVector.text));
+ LONG(SIZEOF(.AlternateResetL2IntVector.text));
+ /* Entry 3 */
+ LONG(LOADADDR(.LpsramCode.text));
+ LONG(ADDR(.LpsramCode.text));
+ LONG(SIZEOF(.LpsramCode.text));
+ _loader_storage_manifest_end = ABSOLUTE(.);
+ } >ram :ram_phdr
+
.bss (NOLOAD) : ALIGN(4096)
{
. = ALIGN(4096);
@@ -503,4 +590,14 @@
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
+
+ .static_uuid_entries (COPY) : ALIGN(1024)
+ {
+ *(*.static_uuids)
+ } > static_uuid_entries_seg :static_uuid_entries_phdr
+
+ .static_log_entries (COPY) : ALIGN(1024)
+ {
+ *(*.static_log*)
+ } > static_log_entries_seg :static_log_entries_phdr
}
diff --git a/soc/xtensa/intel_adsp/common/CMakeLists.txt b/soc/xtensa/intel_adsp/common/CMakeLists.txt
new file mode 100644
index 0000000..aaf9ad1
--- /dev/null
+++ b/soc/xtensa/intel_adsp/common/CMakeLists.txt
@@ -0,0 +1,33 @@
+# Intel CAVS SoC family CMake file
+#
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_interface_library_named(INTEL_ADSP_COMMON)
+
+zephyr_library_named(intel_adsp_common)
+zephyr_library_include_directories(include)
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+
+set_source_files_properties(adsp.c PROPERTIES COMPILE_FLAGS -std=gnu99)
+zephyr_library_sources(adsp.c)
+
+zephyr_library_sources(main_entry.S)
+zephyr_library_sources(soc.c)
+zephyr_library_sources(soc_mp.c)
+zephyr_library_sources(printk_out.c)
+
+zephyr_library_link_libraries(INTEL_ADSP_COMMON)
+
+target_include_directories(INTEL_ADSP_COMMON INTERFACE include)
+target_link_libraries(INTEL_ADSP_COMMON INTERFACE intel_adsp_common)
+
+# Common CAVS code
+if(CONFIG_SOC_SERIES_INTEL_CAVS_V15 OR
+ CONFIG_SOC_SERIES_INTEL_CAVS_V18 OR
+ CONFIG_SOC_SERIES_INTEL_CAVS_V20 OR
+ CONFIG_SOC_SERIES_INTEL_CAVS_V25)
+ zephyr_library_sources(soc.c)
+ zephyr_library_sources(soc_mp.c)
+ include(bootloader.cmake)
+endif()
diff --git a/soc/xtensa/intel_adsp/common/adsp.c b/soc/xtensa/intel_adsp/common/adsp.c
new file mode 100644
index 0000000..257e978
--- /dev/null
+++ b/soc/xtensa/intel_adsp/common/adsp.c
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright(c) 2018 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ * Keyon Jie <yang.jie@linux.intel.com>
+ * Rander Wang <rander.wang@intel.com>
+ * Janusz Jankowski <janusz.jankowski@linux.intel.com>
+ */
+#include <device.h>
+#include <init.h>
+
+#include <logging/log.h>
+LOG_MODULE_REGISTER(sof);
+
+#include <ipc.h>
+#include <soc/shim.h>
+#include <adsp/io.h>
+
+#include <cavs/mailbox.h>
+
+#define SRAM_WINDOW_HOST_OFFSET(x) (0x80000 + x * 0x20000)
+
+static const struct adsp_ipc_fw_ready fw_ready_apl
+ __attribute__((section(".fw_ready"))) __attribute__((used)) = {
+ .hdr = {
+ .cmd = ADSP_IPC_FW_READY,
+ .size = sizeof(struct adsp_ipc_fw_ready),
+ },
+ .version = {
+ .hdr.size = sizeof(struct adsp_ipc_fw_version),
+ .micro = 0,
+ .minor = 1,
+ .major = 0,
+
+ .build = 0,
+ .date = __DATE__,
+ .time = __TIME__,
+
+ .tag = "zephyr",
+ .abi_version = 0,
+ },
+ .flags = 0,
+};
+
+#define NUM_WINDOWS 2
+
+static const struct adsp_ipc_window sram_window = {
+ .ext_hdr = {
+ .hdr.cmd = ADSP_IPC_FW_READY,
+ .hdr.size = sizeof(struct adsp_ipc_window) +
+ sizeof(struct adsp_ipc_window_elem) * NUM_WINDOWS,
+ .type = ADSP_IPC_EXT_WINDOW,
+ },
+ .num_windows = NUM_WINDOWS,
+ .window = {
+ {
+ .type = ADSP_IPC_REGION_REGS,
+ .id = 0, /* map to host window 0 */
+ .flags = 0,
+ .size = MAILBOX_SW_REG_SIZE,
+ .offset = 0,
+ },
+ {
+ .type = ADSP_IPC_REGION_TRACE,
+ .id = 3, /* map to host window 3 */
+ .flags = 0,
+ .size = MAILBOX_TRACE_SIZE,
+ .offset = 0,
+ },
+ },
+};
+
+/*
+ * Sets up the host windows so that the host can see the memory
+ * content on the DSP SRAM.
+ */
+static void prepare_host_windows(void)
+{
+ /* window0, for fw status */
+ sys_write32((HP_SRAM_WIN0_SIZE | 0x7), DMWLO(0));
+ sys_write32((HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE),
+ DMWBA(0));
+ memset((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END), 0,
+ HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
+ SOC_DCACHE_FLUSH((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
+ HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
+
+ /* window3, for trace
+ * zeroed by trace initialization
+ */
+ sys_write32((HP_SRAM_WIN3_SIZE | 0x7), DMWLO(3));
+ sys_write32((HP_SRAM_WIN3_BASE | DMWBA_READONLY | DMWBA_ENABLE),
+ DMWBA(3));
+ memset((void *)HP_SRAM_WIN3_BASE, 0, HP_SRAM_WIN3_SIZE);
+ SOC_DCACHE_FLUSH((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
+}
+
+/*
+ * Sends the firmware ready message so the firmware loader can
+ * map the host windows.
+ */
+static void send_fw_ready(void)
+{
+ memcpy((void *)MAILBOX_DSPBOX_BASE,
+ &fw_ready_apl, sizeof(fw_ready_apl));
+
+ memcpy((void *)(MAILBOX_DSPBOX_BASE + sizeof(fw_ready_apl)),
+ &sram_window, sizeof(sram_window));
+
+ SOC_DCACHE_FLUSH((void *)MAILBOX_DSPBOX_BASE, MAILBOX_DSPBOX_SIZE);
+
+#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
+ sys_write32(SRAM_WINDOW_HOST_OFFSET(0) >> 12,
+ IPC_HOST_BASE + IPC_DIPCIE);
+ sys_write32(0x80000000 | ADSP_IPC_FW_READY,
+ IPC_HOST_BASE + IPC_DIPCI);
+#else
+ sys_write32(SRAM_WINDOW_HOST_OFFSET(0) >> 12,
+ IPC_HOST_BASE + IPC_DIPCIDD);
+ sys_write32(0x80000000 | ADSP_IPC_FW_READY,
+ IPC_HOST_BASE + IPC_DIPCIDR);
+#endif
+}
+
+static int adsp_init(const struct device *dev)
+{
+ prepare_host_windows();
+
+ send_fw_ready();
+
+ return 0;
+}
+
+/* Init after IPM initialization and before logging (uses memory windows) */
+SYS_INIT(adsp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/xtensa/intel_apl_adsp/common/bootloader.cmake b/soc/xtensa/intel_adsp/common/bootloader.cmake
similarity index 96%
rename from soc/xtensa/intel_apl_adsp/common/bootloader.cmake
rename to soc/xtensa/intel_adsp/common/bootloader.cmake
index a796b2e..ba26b2e 100644
--- a/soc/xtensa/intel_apl_adsp/common/bootloader.cmake
+++ b/soc/xtensa/intel_adsp/common/bootloader.cmake
@@ -2,7 +2,7 @@
#
# SPDX-License-Identifier: Apache-2.0
-set(SOC_FAMILY intel_apl_adsp)
+set(SOC_FAMILY intel_adsp)
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/bootloader/CMakeLists.txt)
if(USING_OUT_OF_TREE_BOARD)
diff --git a/soc/xtensa/intel_adsp/common/bootloader/CMakeLists.txt b/soc/xtensa/intel_adsp/common/bootloader/CMakeLists.txt
new file mode 100644
index 0000000..50e939f
--- /dev/null
+++ b/soc/xtensa/intel_adsp/common/bootloader/CMakeLists.txt
@@ -0,0 +1,82 @@
+# Copyright (c) 2019 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# TODO: Need to unbind SOF module.
+
+add_library(base_module base_module.c)
+target_include_directories(base_module PUBLIC
+ ${SOC_DIR}/${ARCH}/${SOC_PATH}/include
+ ${SOC_DIR}/${ARCH}/${SOC_PATH}/../common/include
+ ${ZEPHYR_BASE}/../modules/hal/xtensa/include
+ ${ZEPHYR_BASE}/build/zephyr/include/generated
+ ${ZEPHYR_BASE}/../modules/audio/sof/zephyr/include
+ )
+
+add_library(boot_module boot_module.c)
+target_include_directories(boot_module PUBLIC
+ ${SOC_DIR}/${ARCH}/${SOC_PATH}/include
+ ${SOC_DIR}/${ARCH}/${SOC_PATH}/../common/include
+ ${ZEPHYR_BASE}/../modules/hal/xtensa/include
+ ${ZEPHYR_BASE}/build/zephyr/include/generated
+ ${ZEPHYR_BASE}/../modules/audio/sof/zephyr/include
+ )
+
+add_executable(bootloader
+ boot_entry.S
+ ${ARCH_DIR}/${ARCH}/core/startup/memctl_default.S
+ ${ARCH_DIR}/${ARCH}/core/startup/memerror-vector.S
+ ${ARCH_DIR}/${ARCH}/core/startup/reset-vector.S
+ boot_loader.c
+ start_address.S
+ )
+
+add_dependencies(bootloader ${SYSCALL_LIST_H_TARGET})
+
+set(zephyr_sdk $ENV{ZEPHYR_SDK_INSTALL_DIR})
+
+target_include_directories(bootloader PUBLIC
+ ./
+ ${ZEPHYR_BASE}/include
+ ${TOOLCHAIN_INCLUDES}
+ ${SOC_DIR}/${ARCH}/${SOC_PATH}/
+ ${SOC_DIR}/${ARCH}/${SOC_PATH}/include
+ ${ZEPHYR_BASE}/build/zephyr/include/generated
+ ${ZEPHYR_BASE}/../modules/audio/sof/zephyr/include
+ )
+
+# TODO: pre-process linker script. How do we use toplevel infrastructure ??
+set(bootloader_linker_script "boot_ldr")
+add_custom_command(TARGET bootloader
+ PRE_LINK
+ DEPENDS ${bootloader_linker_script}.x
+ COMMENT "Generating Bootloader!!!!!!!"
+ COMMAND ${CMAKE_C_COMPILER}
+ -x assembler-with-cpp
+ ${NOSYSDEF_CFLAG}
+ -MD
+ -D_LINKER
+ -D_ASMLANGUAGE
+ -I ${SOC_DIR}/${ARCH}/${SOC_PATH}/include
+ -I ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include
+ ${current_defines}
+ ${linker_pass_define}
+ -E ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/bootloader/${bootloader_linker_script}.x
+ -P # Prevent generation of debug `#line' directives.
+ -o ${bootloader_linker_script}.ld
+ VERBATIM
+ WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
+ )
+
+set_source_files_properties(boot_entry.S PROPERTIES COMPILE_FLAGS -DASSEMBLY)
+set_source_files_properties(${ARCH_DIR}/${ARCH}/core/startup/reset-vector.S PROPERTIES COMPILE_FLAGS -DBOOTLOADER)
+
+target_compile_options(bootloader PUBLIC -fno-inline-functions -mlongcalls -mtext-section-literals -imacros${CMAKE_BINARY_DIR}/zephyr/include/generated/autoconf.h)
+
+target_link_libraries(bootloader PUBLIC -Wl,--no-check-sections -ucall_user_start -Wl,-static -nostdlib)
+target_link_libraries(bootloader PRIVATE -T${CMAKE_BINARY_DIR}/zephyr/${bootloader_linker_script}.ld)
+
+if(CONFIG_XTENSA_HAL)
+ target_link_libraries(bootloader PRIVATE XTENSA_HAL)
+ target_link_libraries(bootloader PRIVATE modules_xtensa_hal)
+endif()
diff --git a/soc/xtensa/intel_apl_adsp/common/bootloader/base_module.c b/soc/xtensa/intel_adsp/common/bootloader/base_module.c
similarity index 96%
rename from soc/xtensa/intel_apl_adsp/common/bootloader/base_module.c
rename to soc/xtensa/intel_adsp/common/bootloader/base_module.c
index 8ce33a2..647735c 100644
--- a/soc/xtensa/intel_apl_adsp/common/bootloader/base_module.c
+++ b/soc/xtensa/intel_adsp/common/bootloader/base_module.c
@@ -7,7 +7,7 @@
*/
#include "manifest.h"
-#include <platform/memory.h>
+#include <soc/memory.h>
/*
* Each module has an entry in the FW manifest header. This is NOT part of
diff --git a/soc/xtensa/intel_apl_adsp/common/bootloader/boot_entry.S b/soc/xtensa/intel_adsp/common/bootloader/boot_entry.S
similarity index 97%
rename from soc/xtensa/intel_apl_adsp/common/bootloader/boot_entry.S
rename to soc/xtensa/intel_adsp/common/bootloader/boot_entry.S
index 1fc1a36..6c6b66c 100644
--- a/soc/xtensa/intel_apl_adsp/common/bootloader/boot_entry.S
+++ b/soc/xtensa/intel_adsp/common/bootloader/boot_entry.S
@@ -13,8 +13,9 @@
* 2) Stack is in first HPSRAM bank.
*/
-#include <platform/shim.h>
-#include <platform/platform.h>
+#include <soc/shim.h>
+#include <soc/platform.h>
+#include <soc/memory.h>
#include <xtensa/corebits.h>
#include <xtensa/config/core-isa.h>
@@ -204,7 +205,7 @@
/* determine core we are running on */
rsr.prid a2
- movi a3, PLATFORM_MASTER_CORE_ID
+ movi a3, PLATFORM_PRIMARY_CORE_ID
beq a2, a3, 1f
/* no core should get here */
diff --git a/soc/xtensa/intel_apl_adsp/common/bootloader/boot_ldr.x b/soc/xtensa/intel_adsp/common/bootloader/boot_ldr.x
similarity index 90%
rename from soc/xtensa/intel_apl_adsp/common/bootloader/boot_ldr.x
rename to soc/xtensa/intel_adsp/common/bootloader/boot_ldr.x
index e1abd82..b6cf339 100644
--- a/soc/xtensa/intel_apl_adsp/common/bootloader/boot_ldr.x
+++ b/soc/xtensa/intel_adsp/common/bootloader/boot_ldr.x
@@ -1,29 +1,32 @@
OUTPUT_ARCH(xtensa)
+
+#include <soc/memory.h>
+
PROVIDE(__memctl_default = 0x00000000);
PROVIDE(_MemErrorHandler = 0x00000000);
MEMORY
{
boot_entry_text :
- org = 0xB000A000,
- len = 0x86
+ org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,
+ len = IMR_BOOT_LDR_TEXT_ENTRY_SIZE
boot_entry_lit :
- org = (0xB000A000 + 0x86),
- len = 0x70
+ org = IMR_BOOT_LDR_LIT_BASE,
+ len = IMR_BOOT_LDR_LIT_SIZE
sof_text :
- org = ((0xB000A000 + 0x86) + 0x70),
- len = 0x1C00,
+ org = IMR_BOOT_LDR_TEXT_BASE,
+ len = IMR_BOOT_LDR_TEXT_SIZE,
sof_data :
- org = 0xB0002000,
- len = 0x1000
+ org = IMR_BOOT_LDR_DATA_BASE,
+ len = IMR_BOOT_LDR_DATA_SIZE
sof_bss_data :
- org = 0xB0100000,
- len = 0x10000
+ org = IMR_BOOT_LDR_BSS_BASE,
+ len = IMR_BOOT_LDR_BSS_SIZE
sof_stack :
- org = 0xBE000000,
- len = (1 * 0x1000)
+ org = BOOT_LDR_STACK_BASE,
+ len = BOOT_LDR_STACK_SIZE
wnd0 :
- org = ((((((0xBE000000 + 0x8000) + 0x2000) + 0x800) + 0x800) + 0x1000) + 0x2000),
- len = (0x1000 + 0x1000)
+ org = HP_SRAM_WIN0_BASE,
+ len = HP_SRAM_WIN0_SIZE
}
PHDRS
{
diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
new file mode 100644
index 0000000..86699b87b
--- /dev/null
+++ b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
@@ -0,0 +1,347 @@
+/*
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+#include <cavs/version.h>
+
+#include <soc/platform.h>
+#include <soc/memory.h>
+#include <soc/shim.h>
+#include <adsp/io.h>
+#include <soc.h>
+#include "manifest.h"
+
+#if CONFIG_SOC_INTEL_S1000
+#define MANIFEST_BASE BOOT_LDR_MANIFEST_BASE
+#else
+#define MANIFEST_BASE IMR_BOOT_LDR_MANIFEST_BASE
+#endif
+
+extern void __start(void);
+
+#if !defined(CONFIG_SOC_INTEL_S1000)
+#define MANIFEST_SEGMENT_COUNT 3
+
+static inline void idelay(int n)
+{
+ while (n--) {
+ __asm__ volatile("nop");
+ }
+}
+
+/* generic string compare cloned into the bootloader to
+ * compact code and make it more readable
+ */
+int strcmp(const char *s1, const char *s2)
+{
+ while (*s1 != 0 && *s2 != 0) {
+ if (*s1 < *s2)
+ return -1;
+ if (*s1 > *s2)
+ return 1;
+ s1++;
+ s2++;
+ }
+
+ /* did both string end */
+ if (*s1 != 0)
+ return 1;
+ if (*s2 != 0)
+ return -1;
+
+ /* match */
+ return 0;
+}
+
+/* memcopy used by boot loader */
+static inline void bmemcpy(void *dest, void *src, size_t bytes)
+{
+ uint32_t *d = dest;
+ uint32_t *s = src;
+ int i;
+
+ for (i = 0; i < (bytes >> 2); i++)
+ d[i] = s[i];
+
+ SOC_DCACHE_FLUSH(dest, bytes);
+}
+
+/* bzero used by bootloader */
+static inline void bbzero(void *dest, size_t bytes)
+{
+ uint32_t *d = dest;
+ int i;
+
+ for (i = 0; i < (bytes >> 2); i++)
+ d[i] = 0;
+
+ SOC_DCACHE_FLUSH(dest, bytes);
+}
+
+static void parse_module(struct sof_man_fw_header *hdr,
+ struct sof_man_module *mod)
+{
+ int i;
+ uint32_t bias;
+
+ /* each module has 3 segments */
+ for (i = 0; i < MANIFEST_SEGMENT_COUNT; i++) {
+
+ switch (mod->segment[i].flags.r.type) {
+ case SOF_MAN_SEGMENT_TEXT:
+ case SOF_MAN_SEGMENT_DATA:
+ bias = (mod->segment[i].file_offset -
+ SOF_MAN_ELF_TEXT_OFFSET);
+
+ /* copy from IMR to SRAM */
+ bmemcpy((void *)mod->segment[i].v_base_addr,
+ (void *)((int)hdr + bias),
+ mod->segment[i].flags.r.length *
+ HOST_PAGE_SIZE);
+ break;
+ case SOF_MAN_SEGMENT_BSS:
+ /* copy from IMR to SRAM */
+ bbzero((void *)mod->segment[i].v_base_addr,
+ mod->segment[i].flags.r.length *
+ HOST_PAGE_SIZE);
+ break;
+ default:
+ /* ignore */
+ break;
+ }
+ }
+}
+
+/* On Sue Creek the boot loader is attached separately, no need to skip it */
+#if CONFIG_SOC_INTEL_S1000
+#define MAN_SKIP_ENTRIES 0
+#else
+#define MAN_SKIP_ENTRIES 1
+#endif
+
+static uint32_t get_fw_size_in_use(void)
+{
+ struct sof_man_fw_desc *desc =
+ (struct sof_man_fw_desc *)MANIFEST_BASE;
+ struct sof_man_fw_header *hdr = &desc->header;
+ struct sof_man_module *mod;
+ uint32_t fw_size_in_use = 0xffffffff;
+ int i;
+
+ /* Calculate fw size passed in BASEFW module in MANIFEST */
+ for (i = MAN_SKIP_ENTRIES; i < hdr->num_module_entries; i++) {
+ mod = (struct sof_man_module *)((char *)desc +
+ SOF_MAN_MODULE_OFFSET(i));
+ if (strcmp((char *)mod->name, "BASEFW"))
+ continue;
+ for (i = 0; i < MANIFEST_SEGMENT_COUNT; i++) {
+ if (mod->segment[i].flags.r.type
+ == SOF_MAN_SEGMENT_BSS) {
+ fw_size_in_use = mod->segment[i].v_base_addr
+ - HP_SRAM_BASE
+ + (mod->segment[i].flags.r.length
+ * HOST_PAGE_SIZE);
+ }
+ }
+ }
+
+ return fw_size_in_use;
+}
+
+/* parse FW manifest and copy modules */
+static void parse_manifest(void)
+{
+ struct sof_man_fw_desc *desc =
+ (struct sof_man_fw_desc *)MANIFEST_BASE;
+ struct sof_man_fw_header *hdr = &desc->header;
+ struct sof_man_module *mod;
+ int i;
+
+ /* copy module to SRAM - skip bootloader module */
+ for (i = MAN_SKIP_ENTRIES; i < hdr->num_module_entries; i++) {
+
+ mod = (void *)((uintptr_t)desc + SOF_MAN_MODULE_OFFSET(i));
+ parse_module(hdr, mod);
+ }
+}
+#endif
+
+#if CAVS_VERSION >= CAVS_VERSION_1_8
+/* function powers up a number of memory banks provided as an argument and
+ * gates remaining memory banks
+ */
+static int32_t hp_sram_pm_banks(uint32_t banks)
+{
+ int delay_count = 256;
+ uint32_t status;
+ uint32_t ebb_mask0, ebb_mask1, ebb_avail_mask0, ebb_avail_mask1;
+ uint32_t total_banks_count = PLATFORM_HPSRAM_EBB_COUNT;
+
+ shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_ON);
+
+ /* add some delay before touch power register */
+ idelay(delay_count);
+
+ /* bit masks reflect total number of available EBB (banks) in each
+ * segment; current implementation supports 2 segments 0,1
+ */
+ if (total_banks_count > EBB_SEGMENT_SIZE) {
+ ebb_avail_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0);
+ ebb_avail_mask1 = (uint32_t)GENMASK(total_banks_count -
+ EBB_SEGMENT_SIZE - 1, 0);
+ } else{
+ ebb_avail_mask0 = (uint32_t)GENMASK(total_banks_count - 1,
+ 0);
+ ebb_avail_mask1 = 0;
+ }
+
+ /* bit masks of banks that have to be powered up in each segment */
+ if (banks > EBB_SEGMENT_SIZE) {
+ ebb_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0);
+ ebb_mask1 = (uint32_t)GENMASK(banks - EBB_SEGMENT_SIZE - 1,
+ 0);
+ } else{
+ /* assumption that ebb_in_use is > 0 */
+ ebb_mask0 = (uint32_t)GENMASK(banks - 1, 0);
+ ebb_mask1 = 0;
+ }
+
+ /* HSPGCTL, HSRMCTL use reverse logic - 0 means EBB is power gated */
+ io_reg_write(HSPGCTL0, (~ebb_mask0) & ebb_avail_mask0);
+ io_reg_write(HSRMCTL0, (~ebb_mask0) & ebb_avail_mask0);
+ io_reg_write(HSPGCTL1, (~ebb_mask1) & ebb_avail_mask1);
+ io_reg_write(HSRMCTL1, (~ebb_mask1) & ebb_avail_mask1);
+
+ /* query the power status of first part of HP memory */
+ /* to check whether it has been powered up. A few */
+ /* cycles are needed for it to be powered up */
+ status = io_reg_read(HSPGISTS0);
+ while (status != ((~ebb_mask0) & ebb_avail_mask0)) {
+ idelay(delay_count);
+ status = io_reg_read(HSPGISTS0);
+ }
+ /* query the power status of second part of HP memory */
+ /* and do as above code */
+
+ status = io_reg_read(HSPGISTS1);
+ while (status != ((~ebb_mask1) & ebb_avail_mask1)) {
+ idelay(delay_count);
+ status = io_reg_read(HSPGISTS1);
+ }
+ /* add some delay before touch power register */
+ idelay(delay_count);
+
+ shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_BYPASS);
+
+ return 0;
+}
+
+static uint32_t hp_sram_power_on_memory(uint32_t memory_size)
+{
+ uint32_t ebb_in_use;
+
+ /* calculate total number of used SRAM banks (EBB)
+ * to power up only necessary banks
+ */
+ ebb_in_use = (!(memory_size % SRAM_BANK_SIZE)) ?
+ (memory_size / SRAM_BANK_SIZE) :
+ (memory_size / SRAM_BANK_SIZE) + 1;
+
+ return hp_sram_pm_banks(ebb_in_use);
+}
+
+static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size)
+{
+ /* keep enabled only memory banks used by FW */
+ return hp_sram_power_on_memory(memory_size);
+}
+
+static int32_t hp_sram_init(void)
+{
+ return hp_sram_power_on_memory(HP_SRAM_SIZE);
+}
+
+#else
+
+static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size)
+{
+ return 0;
+}
+
+static uint32_t hp_sram_init(void)
+{
+ return 0;
+}
+
+#endif
+
+static int32_t lp_sram_init(void)
+{
+ uint32_t status;
+ uint32_t lspgctl_value;
+ uint32_t timeout_counter, delay_count = 256;
+
+ timeout_counter = delay_count;
+
+ shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_ON);
+
+ /* add some delay before writing power registers */
+ idelay(delay_count);
+
+ lspgctl_value = shim_read(SHIM_LSPGISTS);
+ shim_write(SHIM_LSPGCTL, lspgctl_value & ~LPSRAM_MASK(0));
+
+ /* add some delay before checking the status */
+ idelay(delay_count);
+
+ /* query the power status of first part of LP memory */
+ /* to check whether it has been powered up. A few */
+ /* cycles are needed for it to be powered up */
+ status = io_reg_read(LSPGISTS);
+ while (status) {
+ if (!timeout_counter--) {
+ break;
+ }
+ idelay(delay_count);
+ status = io_reg_read(LSPGISTS);
+ }
+
+ shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_BYPASS);
+
+ return status;
+}
+
+/* boot master core */
+void boot_master_core(void)
+{
+ int32_t result;
+
+
+ /* init the HPSRAM */
+ result = hp_sram_init();
+ if (result < 0) {
+ return;
+ }
+
+ /* init the LPSRAM */
+
+ result = lp_sram_init();
+ if (result < 0) {
+ return;
+ }
+
+#if !defined(CONFIG_SOC_INTEL_S1000)
+ /* parse manifest and copy modules */
+ parse_manifest();
+
+ hp_sram_power_off_unused_banks(get_fw_size_in_use());
+#endif
+ /* now call SOF entry */
+ __start();
+}
diff --git a/soc/xtensa/intel_apl_adsp/common/bootloader/boot_module.c b/soc/xtensa/intel_adsp/common/bootloader/boot_module.c
similarity index 96%
rename from soc/xtensa/intel_apl_adsp/common/bootloader/boot_module.c
rename to soc/xtensa/intel_adsp/common/bootloader/boot_module.c
index 5ce47ad..701c022 100644
--- a/soc/xtensa/intel_apl_adsp/common/bootloader/boot_module.c
+++ b/soc/xtensa/intel_adsp/common/bootloader/boot_module.c
@@ -7,7 +7,7 @@
*/
#include "manifest.h"
-#include <platform/memory.h>
+#include <soc/memory.h>
/*
* Each module has an entry in the FW manifest header. This is NOT part of
diff --git a/soc/xtensa/intel_apl_adsp/common/bootloader/manifest.h b/soc/xtensa/intel_adsp/common/bootloader/manifest.h
similarity index 100%
rename from soc/xtensa/intel_apl_adsp/common/bootloader/manifest.h
rename to soc/xtensa/intel_adsp/common/bootloader/manifest.h
diff --git a/soc/xtensa/intel_apl_adsp/common/bootloader/start_address.S b/soc/xtensa/intel_adsp/common/bootloader/start_address.S
similarity index 82%
rename from soc/xtensa/intel_apl_adsp/common/bootloader/start_address.S
rename to soc/xtensa/intel_adsp/common/bootloader/start_address.S
index 0089c0c..fa33ba4 100644
--- a/soc/xtensa/intel_apl_adsp/common/bootloader/start_address.S
+++ b/soc/xtensa/intel_adsp/common/bootloader/start_address.S
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
-#include <platform/memory.h>
+#include <soc/memory.h>
.global _start
.equ _start, SOF_TEXT_BASE
diff --git a/soc/xtensa/intel_adsp/common/fix_elf_addrs.py b/soc/xtensa/intel_adsp/common/fix_elf_addrs.py
new file mode 100755
index 0000000..e7b1118
--- /dev/null
+++ b/soc/xtensa/intel_adsp/common/fix_elf_addrs.py
@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+#
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# ADSP devices have their RAM regions mapped twice, once in the 512MB
+# region from 0x80000000-0x9fffffff and again from
+# 0xa0000000-0xbfffffff. The first mapping is set in the CPU to
+# bypass the L1 cache, and so access through pointers in that region
+# is coherent between CPUs (but slow). The second region accesses the
+# same memory through the L1 cache and requires careful flushing when
+# used with shared data.
+#
+# This distinction is exposed in the linker script, where some symbols
+# (e.g. stack regions) are linked into cached memory, but others
+# (general kernel memory) are not. But the rimage signing tool
+# doesn't understand that and fails if regions aren't contiguous.
+#
+# Walk the sections in the ELF file, changing the VMA/LMA of each
+# uncached section to the equivalent address in the cached area of
+# memory.
+
+import os
+import sys
+from elftools.elf.elffile import ELFFile
+
+objcopy_bin = sys.argv[1]
+elffile = sys.argv[2]
+
+fixup =[]
+with open(elffile, "rb") as fd:
+ elf = ELFFile(fd)
+ for s in elf.iter_sections():
+ addr = s.header.sh_addr
+ if addr >= 0x80000000 and addr < 0xa0000000:
+ print(f"fix_elf_addrs.py: Moving section {s.name} to cached SRAM region")
+ fixup.append(s.name)
+
+for s in fixup:
+ cmd = f"{objcopy_bin} --change-section-address {s}+0x20000000 {elffile}"
+ print(cmd)
+ os.system(cmd)
diff --git a/soc/xtensa/intel_adsp/common/include/adsp/cache.h b/soc/xtensa/intel_adsp/common/include/adsp/cache.h
new file mode 100644
index 0000000..63075ab
--- /dev/null
+++ b/soc/xtensa/intel_adsp/common/include/adsp/cache.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2019 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __COMMON_ADSP_CACHE_H__
+#define __COMMON_ADSP_CACHE_H__
+
+#include <xtensa/hal.h>
+
+/* macros for data cache operations */
+#define SOC_DCACHE_FLUSH(addr, size) \
+ xthal_dcache_region_writeback((addr), (size))
+#define SOC_DCACHE_INVALIDATE(addr, size) \
+ xthal_dcache_region_invalidate((addr), (size))
+
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/io.h b/soc/xtensa/intel_adsp/common/include/adsp/io.h
similarity index 67%
rename from soc/xtensa/intel_apl_adsp/include/platform/io.h
rename to soc/xtensa/intel_adsp/common/include/adsp/io.h
index 0fbe4bc..727fa03 100644
--- a/soc/xtensa/intel_apl_adsp/include/platform/io.h
+++ b/soc/xtensa/intel_adsp/common/include/adsp/io.h
@@ -10,6 +10,7 @@
#define __INCLUDE_IO__
#include <stdint.h>
+#include <soc/memory.h>
#include <sys/sys_io.h>
#include <arch/common/sys_io.h>
@@ -41,4 +42,24 @@
sys_write16(val, reg);
}
+static inline uint32_t shim_read(uint32_t reg)
+{
+ return sys_read32(SHIM_BASE + reg);
+}
+
+static inline void shim_write(uint32_t reg, uint32_t val)
+{
+ sys_write32(val, (SHIM_BASE + reg));
+}
+
+static inline uint64_t shim_read64(uint32_t reg)
+{
+ return *((volatile uint64_t*)(SHIM_BASE + reg));
+}
+
+static inline void shim_write64(uint32_t reg, uint64_t val)
+{
+ *((volatile uint64_t*)(SHIM_BASE + reg)) = val;
+}
+
#endif
diff --git a/soc/xtensa/intel_adsp/common/include/cavs/cpu.h b/soc/xtensa/intel_adsp/common/include/cavs/cpu.h
new file mode 100644
index 0000000..a3b1a1a
--- /dev/null
+++ b/soc/xtensa/intel_adsp/common/include/cavs/cpu.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright(c) 2019 Intel Corporation. All rights reserved.
+ *
+ * Author: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
+ */
+
+/**
+ * \file cavs/lib/cpu.h
+ * \brief DSP parameters, common for cAVS platforms.
+ */
+
+#ifndef __CAVS_CPU_H__
+#define __CAVS_CPU_H__
+
+/** \brief Number of available DSP cores (conf. by kconfig) */
+#define PLATFORM_CORE_COUNT (defined(CONFIG_SMP) ? CONFIG_MP_NUM_CPUS : 1)
+
+/** Id of master DSP core */
+#define PLATFORM_PRIMARY_CORE_ID 0
+
+#endif /* __CAVS_CPU_H__ */
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/mailbox.h b/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h
similarity index 68%
rename from soc/xtensa/intel_apl_adsp/include/platform/mailbox.h
rename to soc/xtensa/intel_adsp/common/include/cavs/mailbox.h
index 6cfff98..fe06ab6 100644
--- a/soc/xtensa/intel_apl_adsp/include/platform/mailbox.h
+++ b/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h
@@ -1,15 +1,16 @@
/* SPDX-License-Identifier: Apache-2.0
*
- * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ * Copyright(c) 2019 Intel Corporation. All rights reserved.
*
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
* Keyon Jie <yang.jie@linux.intel.com>
*/
-#ifndef __INCLUDE_PLATFORM_MAILBOX__
-#define __INCLUDE_PLATFORM_MAILBOX__
+#ifndef __CAVS_MAILBOX_H__
+#define __CAVS_MAILBOX_H__
-#include <platform/memory.h>
+#include <stddef.h>
+#include <stdint.h>
/*
* The Window Region on HPSRAM for cAVS platforms is organised like this :-
@@ -28,19 +29,19 @@
* +---------------------+----------------+-----------------------------------+
*
* Note: For suecreek SRAM_SW_REG window does not exist - MAILBOX_SW_REG_BASE
- * and MAILBOX_SW_REG_BASE are equal to 0
+ * and MAILBOX_SW_REG_BASE are equal to 0
*/
/* window 3 - trace */
-#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
-#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
+#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
+#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
/* window 2 debug, exception and stream */
-#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE
-#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
+#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE
+#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
-#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE
-#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE
+#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE
+#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE
#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE
#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE
@@ -48,14 +49,14 @@
#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE)
/* window 1 inbox/downlink and FW registers */
-#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
-#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
+#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
+#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
/* window 0 */
-#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
-#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
+#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
+#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
-#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE
-#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE
+#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE
+#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE
-#endif
+#endif /* __CAVS_MAILBOX_H__ */
diff --git a/soc/xtensa/intel_adsp/common/include/cavs/version.h b/soc/xtensa/intel_adsp/common/include/cavs/version.h
new file mode 100644
index 0000000..0ac2fbc
--- /dev/null
+++ b/soc/xtensa/intel_adsp/common/include/cavs/version.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright(c) 2018 Intel Corporation. All rights reserved.
+ *
+ * Author: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
+ */
+
+#ifndef __CAVS_VERSION_H__
+#define __CAVS_VERSION_H__
+
+#include <autoconf.h>
+
+#define CAVS_VERSION_1_5 0x10500
+#define CAVS_VERSION_1_8 0x10800
+#define CAVS_VERSION_2_0 0x20000
+#define CAVS_VERSION_2_5 0x20500
+
+/* CAVS version defined by CONFIG_CAVS_VER_*/
+#if CONFIG_SOC_SERIES_INTEL_CAVS_V15
+#define CAVS_VERSION CAVS_VERSION_1_5
+#elif CONFIG_SOC_SERIES_INTEL_CAVS_V18
+#define CAVS_VERSION CAVS_VERSION_1_8
+#elif CONFIG_SOC_SERIES_INTEL_CAVS_V20
+#define CAVS_VERSION CAVS_VERSION_2_0
+#elif CONFIG_SOC_SERIES_INTEL_CAVS_V25
+#define CAVS_VERSION CAVS_VERSION_2_5
+#endif
+
+#endif /* __CAVS_VERSION_H__ */
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/ipc.h b/soc/xtensa/intel_adsp/common/include/ipc.h
similarity index 100%
rename from soc/xtensa/intel_apl_adsp/include/platform/ipc.h
rename to soc/xtensa/intel_adsp/common/include/ipc.h
diff --git a/soc/xtensa/intel_apl_adsp/soc.h b/soc/xtensa/intel_adsp/common/include/soc.h
similarity index 61%
rename from soc/xtensa/intel_apl_adsp/soc.h
rename to soc/xtensa/intel_adsp/common/include/soc.h
index 8e06af8..0cfbf08 100644
--- a/soc/xtensa/intel_apl_adsp/soc.h
+++ b/soc/xtensa/intel_adsp/common/include/soc.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019 Intel Corporation
+ *
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,7 +9,7 @@
#include <sys/sys_io.h>
-#include "memory.h"
+#include <adsp/cache.h>
#ifndef __INC_SOC_H
#define __INC_SOC_H
@@ -47,44 +48,6 @@
#define IOAPIC_EDGE 0
#define IOAPIC_HIGH 0
-/* low power DMACs */
-#define LP_GP_DMA_SIZE 0x00001000
-#define DW_DMA0_BASE_ADDR 0x0000C000
-#define DW_DMA1_BASE_ADDR (0x0000C000 +\
- 1 * LP_GP_DMA_SIZE)
-#define DW_DMA2_BASE_ADDR (0x0000C000 +\
- 2 * LP_GP_DMA_SIZE)
-
-#define DW_DMA0_IRQ 0x00001110
-#define DW_DMA1_IRQ 0x0000010A
-#define DW_DMA2_IRQ 0x0000010D
-
-/* address of DMA ownership register. We need to properly configure
- * this register in order to access the DMA registers.
- */
-#define CAVS_DMA0_OWNERSHIP_REG (0x00071A60)
-#define CAVS_DMA1_OWNERSHIP_REG (0x00071A62)
-#define CAVS_DMA2_OWNERSHIP_REG (0x00071A64)
-
-#define DMA_HANDSHAKE_DMIC_RXA 0
-#define DMA_HANDSHAKE_DMIC_RXB 1
-#define DMA_HANDSHAKE_SSP0_TX 2
-#define DMA_HANDSHAKE_SSP0_RX 3
-#define DMA_HANDSHAKE_SSP1_TX 4
-#define DMA_HANDSHAKE_SSP1_RX 5
-#define DMA_HANDSHAKE_SSP2_TX 6
-#define DMA_HANDSHAKE_SSP2_RX 7
-#define DMA_HANDSHAKE_SSP3_TX 8
-#define DMA_HANDSHAKE_SSP3_RX 9
-
-/* DMA Channel Allocation
- * FIXME: I2S Driver assigns channel in Kconfig.
- * Perhaps DTS is a better option
- */
-#define DMIC_DMA_DEV_NAME CONFIG_DMA_0_NAME
-#define DMA_CHANNEL_DMIC_RXA 0
-#define DMA_CHANNEL_DMIC_RXB 1
-
/* I2S */
#define I2S_CAVS_IRQ(i2s_num) \
SOC_AGGREGATE_IRQ(0, (i2s_num), CAVS_L2_AGG_INT_LEVEL5)
@@ -98,58 +61,8 @@
#define SSP_MN_DIV_BASE(x) \
(0x00078D00 + ((x) * SSP_MN_DIV_SIZE))
-/* MCLK control */
-#define SOC_MCLK_DIV_CTRL_BASE 0x00008E00
-#define SOC_NUM_MCLK_OUTPUTS 2
-#define SOC_MDIVCTRL_MCLK_OUT_EN(mclk) BIT(mclk)
-#define SOC_MDIVXR_SET_DIVIDER_BYPASS BIT_MASK(12)
-
-struct soc_mclk_control_regs {
- uint32_t mdivctrl;
- uint32_t reserved[31];
- uint32_t mdivxr[SOC_NUM_MCLK_OUTPUTS];
-};
-
#define PDM_BASE 0x00010000
-#define SOC_NUM_LPGPDMAC 3
-#define SOC_NUM_CHANNELS_IN_DMAC 8
-
-/* SOC Resource Allocation Registers */
-#define SOC_RESOURCE_ALLOC_REG_BASE 0x00071A60
-/* bit field definition for LP GPDMA ownership register */
-#define SOC_LPGPDMAC_OWNER_DSP \
- (BIT(15) | BIT_MASK(SOC_NUM_CHANNELS_IN_DMAC))
-
-#define SOC_NUM_I2S_INSTANCES 4
-/* bit field definition for IO peripheral ownership register */
-#define SOC_DSPIOP_I2S_OWNSEL_DSP \
- (BIT_MASK(SOC_NUM_I2S_INSTANCES) << 8)
-#define SOC_DSPIOP_DMIC_OWNSEL_DSP BIT(0)
-
-/* bit field definition for general ownership register */
-#define SOC_GENO_TIMESTAMP_OWNER_DSP BIT(2)
-#define SOC_GENO_MNDIV_OWNER_DSP BIT(1)
-
-struct soc_resource_alloc_regs {
- union {
- uint16_t lpgpdmacxo[SOC_NUM_LPGPDMAC];
- uint16_t reserved[4];
- };
- uint32_t dspiopo;
- uint32_t geno;
-};
-
-/* DMIC SHIM Registers */
-#define SOC_DMIC_SHIM_REG_BASE 0x00071E80
-#define SOC_DMIC_SHIM_DMICLCTL_SPA BIT(0)
-#define SOC_DMIC_SHIM_DMICLCTL_CPA BIT(8)
-
-struct soc_dmic_shim_regs {
- uint32_t dmiclcap;
- uint32_t dmiclctl;
-};
-
/* SOC DSP SHIM Registers */
#define SOC_DSP_SHIM_REG_BASE 0x00001000
@@ -244,12 +157,6 @@
uint32_t reserved4[22];
};
-/* macros for data cache operations */
-#define SOC_DCACHE_FLUSH(addr, size) \
- xthal_dcache_region_writeback((addr), (size))
-#define SOC_DCACHE_INVALIDATE(addr, size) \
- xthal_dcache_region_invalidate((addr), (size))
-
extern void z_soc_irq_enable(uint32_t irq);
extern void z_soc_irq_disable(uint32_t irq);
extern int z_soc_irq_is_enabled(unsigned int irq);
diff --git a/soc/xtensa/intel_apl_adsp/main_entry.S b/soc/xtensa/intel_adsp/common/main_entry.S
similarity index 100%
rename from soc/xtensa/intel_apl_adsp/main_entry.S
rename to soc/xtensa/intel_adsp/common/main_entry.S
diff --git a/soc/xtensa/intel_apl_adsp/soc.c b/soc/xtensa/intel_adsp/common/soc.c
similarity index 99%
rename from soc/xtensa/intel_apl_adsp/soc.c
rename to soc/xtensa/intel_adsp/common/soc.c
index 08cf124..f3c5175 100644
--- a/soc/xtensa/intel_apl_adsp/soc.c
+++ b/soc/xtensa/intel_adsp/common/soc.c
@@ -229,7 +229,6 @@
static int soc_init(const struct device *dev)
{
soc_set_power_and_clock();
-
return 0;
}
diff --git a/soc/xtensa/intel_apl_adsp/soc_mp.c b/soc/xtensa/intel_adsp/common/soc_mp.c
similarity index 81%
rename from soc/xtensa/intel_apl_adsp/soc_mp.c
rename to soc/xtensa/intel_adsp/common/soc_mp.c
index 2b0d049..6b05de4 100644
--- a/soc/xtensa/intel_apl_adsp/soc_mp.c
+++ b/soc/xtensa/intel_adsp/common/soc_mp.c
@@ -17,15 +17,17 @@
#include <logging/log.h>
LOG_MODULE_REGISTER(soc_mp, CONFIG_SOC_LOG_LEVEL);
-#include "soc.h"
-#include "memory.h"
+#include <soc.h>
+#include <adsp/io.h>
-#include <platform/shim.h>
+#include <soc/shim.h>
-#ifdef CONFIG_SCHED_IPI_SUPPORTED
#include <drivers/ipm.h>
#include <ipm/ipm_cavs_idc.h>
-#include <ipm/ipm_cavs_idc_priv.h>
+
+#if CONFIG_MP_NUM_CPUS > 1 && !defined(CONFIG_IPM_CAVS_IDC)
+#error Need to enable the IPM driver for multiprocessing
+#endif
/* ROM wake version parsed by ROM during core wake up. */
#define IDC_ROM_WAKE_VERSION 0x2
@@ -50,7 +52,6 @@
#define IDC_MSG_POWER_UP_EXT(x) IDC_EXTENSION((x) >> 2)
static const struct device *idc;
-#endif
extern void __start(void);
@@ -75,20 +76,13 @@
static void mp_entry2(void)
{
- volatile int ps, ie;
+ volatile int ie;
uint32_t idc_reg;
/* Copy over VECBASE from the main CPU for an initial value
* (will need to revisit this if we ever allow a user API to
- * change interrupt vectors at runtime). Make sure interrupts
- * are locally disabled, then synthesize a PS value that will
- * enable them for the user code to pass to irq_unlock()
- * later.
+ * change interrupt vectors at runtime).
*/
- __asm__ volatile("rsr.PS %0" : "=r"(ps));
- ps &= ~(PS_EXCM_MASK | PS_INTLEVEL_MASK);
- __asm__ volatile("wsr.PS %0" : : "r"(ps));
-
ie = 0;
__asm__ volatile("wsr.INTENABLE %0" : : "r"(ie));
__asm__ volatile("wsr.VECBASE %0" : : "r"(start_rec.vecbase));
@@ -101,8 +95,8 @@
"wsr." CONFIG_XTENSA_KERNEL_CPU_PTR_SR " %0" : : "r"(cpu));
/* Clear busy bit set by power up message */
- idc_reg = idc_read(REG_IDCTFC(0), start_rec.cpu) | REG_IDCTFC_BUSY;
- idc_write(REG_IDCTFC(0), start_rec.cpu, idc_reg);
+ idc_reg = idc_read(IPC_IDCTFC(0), start_rec.cpu) | IPC_IDCTFC_BUSY;
+ idc_write(IPC_IDCTFC(0), start_rec.cpu, idc_reg);
#ifdef CONFIG_IPM_CAVS_IDC
/* Interrupt must be enabled while running on current core */
@@ -177,27 +171,27 @@
SOC_DCACHE_FLUSH(&start_rec, sizeof(start_rec));
-#ifdef CONFIG_SCHED_IPI_SUPPORTED
+#ifdef CONFIG_IPM_CAVS_IDC
idc = device_get_binding(DT_LABEL(DT_INST(0, intel_cavs_idc)));
#endif
/* Enable IDC interrupt on the other core */
- idc_reg = idc_read(REG_IDCCTL, cpu_num);
- idc_reg |= REG_IDCCTL_IDCTBIE(0);
- idc_write(REG_IDCCTL, cpu_num, idc_reg);
+ idc_reg = idc_read(IPC_IDCCTL, cpu_num);
+ idc_reg |= IPC_IDCCTL_IDCTBIE(0);
+ idc_write(IPC_IDCCTL, cpu_num, idc_reg);
sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 +
CAVS_ICTL_INT_CPU_OFFSET(cpu_num), 8);
/* Send power up message to the other core */
- idc_write(REG_IDCIETC(cpu_num), 0, IDC_MSG_POWER_UP_EXT(RAM_BASE));
- idc_write(REG_IDCITC(cpu_num), 0, IDC_MSG_POWER_UP | REG_IDCITC_BUSY);
+ idc_write(IPC_IDCIETC(cpu_num), 0, IDC_MSG_POWER_UP_EXT(RAM_BASE));
+ idc_write(IPC_IDCITC(cpu_num), 0, IDC_MSG_POWER_UP | IPC_IDCITC_BUSY);
/* Disable IDC interrupt on other core so IPI won't cause
* them to jump to ISR until the core is fully initialized.
*/
- idc_reg = idc_read(REG_IDCCTL, cpu_num);
- idc_reg &= ~REG_IDCCTL_IDCTBIE(0);
- idc_write(REG_IDCCTL, cpu_num, idc_reg);
+ idc_reg = idc_read(IPC_IDCCTL, cpu_num);
+ idc_reg &= ~IPC_IDCCTL_IDCTBIE(0);
+ idc_write(IPC_IDCCTL, cpu_num, idc_reg);
sys_clear_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 +
CAVS_ICTL_INT_CPU_OFFSET(cpu_num), 8);
@@ -206,8 +200,8 @@
} while (start_rec.alive == 0);
/* Clear done bit from responding the power up message */
- idc_reg = idc_read(REG_IDCIETC(cpu_num), 0) | REG_IDCIETC_DONE;
- idc_write(REG_IDCIETC(cpu_num), 0, idc_reg);
+ idc_reg = idc_read(IPC_IDCIETC(cpu_num), 0) | IPC_IDCIETC_DONE;
+ idc_write(IPC_IDCIETC(cpu_num), 0, idc_reg);
}
#ifdef CONFIG_SCHED_IPI_SUPPORTED
diff --git a/soc/xtensa/intel_apl_adsp/CMakeLists.txt b/soc/xtensa/intel_apl_adsp/CMakeLists.txt
deleted file mode 100644
index be3edac..0000000
--- a/soc/xtensa/intel_apl_adsp/CMakeLists.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library_named(${ARCH}_${SOC_NAME})
-zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
-zephyr_library_sources(adsp.c)
-zephyr_library_sources(soc.c)
-zephyr_library_sources(main_entry.S)
-
-zephyr_library_sources_ifdef(CONFIG_SMP soc_mp.c)
-
-add_subdirectory(common)
diff --git a/soc/xtensa/intel_apl_adsp/common/bootloader/CMakeLists.txt b/soc/xtensa/intel_apl_adsp/common/bootloader/CMakeLists.txt
deleted file mode 100644
index 81a48be..0000000
--- a/soc/xtensa/intel_apl_adsp/common/bootloader/CMakeLists.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-# Copyright (c) 2019 Intel Corporation
-#
-# SPDX-License-Identifier: Apache-2.0
-
-add_library(base_module base_module.c)
-target_include_directories(base_module PUBLIC
- $<TARGET_PROPERTY:${ARCH}_${SOC_NAME},SOURCE_DIR>/include
- )
-
-add_library(boot_module boot_module.c)
-target_include_directories(boot_module PUBLIC
- $<TARGET_PROPERTY:${ARCH}_${SOC_NAME},SOURCE_DIR>/include
- )
-
-add_executable(bootloader
- boot_entry.S
- ${ARCH_DIR}/${ARCH}/core/startup/memctl_default.S
- ${ARCH_DIR}/${ARCH}/core/startup/memerror-vector.S
- ${ARCH_DIR}/${ARCH}/core/startup/reset-vector.S
- boot_loader.c
- start_address.S
- )
-
-add_dependencies(bootloader ${SYSCALL_LIST_H_TARGET})
-
-set(zephyr_sdk ${ZEPHYR_SDK_INSTALL_DIR})
-
-target_include_directories(bootloader PUBLIC
- ./
- ${ZEPHYR_BASE}/include
- ${TOOLCHAIN_INCLUDES}
- $<TARGET_PROPERTY:${ARCH}_${SOC_NAME},SOURCE_DIR>/
- $<TARGET_PROPERTY:${ARCH}_${SOC_NAME},SOURCE_DIR>/include
- )
-
-set_source_files_properties(boot_entry.S PROPERTIES COMPILE_FLAGS -DASSEMBLY)
-set_source_files_properties(${ARCH_DIR}/${ARCH}/core/startup/reset-vector.S PROPERTIES COMPILE_FLAGS -DBOOTLOADER)
-
-target_compile_options(bootloader PUBLIC -fno-inline-functions -mlongcalls -mtext-section-literals -imacros${CMAKE_BINARY_DIR}/zephyr/include/generated/autoconf.h)
-
-target_link_libraries(bootloader PUBLIC -Wl,--no-check-sections -ucall_user_start -Wl,-static -nostdlib)
-target_link_libraries(bootloader PRIVATE -lhal -L${zephyr_sdk}/xtensa/intel_apl_adsp/xtensa-zephyr-elf/lib)
-target_link_libraries(bootloader PRIVATE -T$<TARGET_PROPERTY:${ARCH}_${SOC_NAME},SOURCE_DIR>/common/bootloader/boot_ldr.x)
-
-if(CONFIG_XTENSA_HAL)
- target_link_libraries(bootloader PRIVATE XTENSA_HAL)
-endif()
diff --git a/soc/xtensa/intel_apl_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_apl_adsp/common/bootloader/boot_loader.c
deleted file mode 100644
index c60b668..0000000
--- a/soc/xtensa/intel_apl_adsp/common/bootloader/boot_loader.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright(c) 2016 Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <platform/platform.h>
-#include <platform/memory.h>
-#include <soc.h>
-#include "manifest.h"
-
-#define MANIFEST_BASE IMR_BOOT_LDR_MANIFEST_BASE
-
-extern void __start(void);
-
-static inline void idelay(int n)
-{
- while (n--) {
- __asm__ volatile("nop");
- }
-}
-
-/* memcopy used by boot loader */
-static inline void bmemcpy(void *dest, void *src, size_t bytes)
-{
- uint32_t *d = dest;
- uint32_t *s = src;
- int i;
-
- for (i = 0; i < (bytes >> 2); i++)
- d[i] = s[i];
-
- SOC_DCACHE_FLUSH(dest, bytes);
-}
-
-/* bzero used by bootloader */
-static inline void bbzero(void *dest, size_t bytes)
-{
- uint32_t *d = dest;
- int i;
-
- for (i = 0; i < (bytes >> 2); i++)
- d[i] = 0;
-
- SOC_DCACHE_FLUSH(dest, bytes);
-}
-
-static void parse_module(struct sof_man_fw_header *hdr,
- struct sof_man_module *mod)
-{
- int i;
- uint32_t bias;
-
- /* each module has 3 segments */
- for (i = 0; i < 3; i++) {
-
- /* platform_trace_point(TRACE_BOOT_LDR_PARSE_SEGMENT + i); */
- switch (mod->segment[i].flags.r.type) {
- case SOF_MAN_SEGMENT_TEXT:
- case SOF_MAN_SEGMENT_DATA:
- bias = (mod->segment[i].file_offset -
- SOF_MAN_ELF_TEXT_OFFSET);
-
- /* copy from IMR to SRAM */
- bmemcpy((void *)mod->segment[i].v_base_addr,
- (void *)((int)hdr + bias),
- mod->segment[i].flags.r.length *
- HOST_PAGE_SIZE);
- break;
- case SOF_MAN_SEGMENT_BSS:
- /* copy from IMR to SRAM */
- bbzero((void *)mod->segment[i].v_base_addr,
- mod->segment[i].flags.r.length *
- HOST_PAGE_SIZE);
- break;
- default:
- /* ignore */
- break;
- }
- }
-}
-
-#define MAN_SKIP_ENTRIES 1
-
-/* parse FW manifest and copy modules */
-static void parse_manifest(void)
-{
- struct sof_man_fw_desc *desc =
- (struct sof_man_fw_desc *)MANIFEST_BASE;
- struct sof_man_fw_header *hdr = &desc->header;
- struct sof_man_module *mod;
- int i;
-
- /* copy module to SRAM - skip bootloader module */
- for (i = MAN_SKIP_ENTRIES; i < hdr->num_module_entries; i++) {
-
- /* platform_trace_point(TRACE_BOOT_LDR_PARSE_MODULE + i); */
- mod = (void *)((uintptr_t)desc + SOF_MAN_MODULE_OFFSET(i));
- parse_module(hdr, mod);
- }
-}
-
-static int32_t lp_sram_init(void)
-{
- uint32_t status;
- uint32_t lspgctl_value;
- uint32_t timeout_counter, delay_count = 256;
-
- timeout_counter = delay_count;
-
- shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_ON);
-
- /* add some delay before writing power registers */
- idelay(delay_count);
-
- lspgctl_value = shim_read(LSPGCTL);
- shim_write(LSPGCTL, lspgctl_value & ~LPSRAM_MASK(0));
-
- /* add some delay before checking the status */
- idelay(delay_count);
-
- /* query the power status of first part of LP memory */
- /* to check whether it has been powered up. A few */
- /* cycles are needed for it to be powered up */
- status = io_reg_read(LSPGISTS);
- while (status) {
- if (!timeout_counter--) {
- /* platform_panic(SOF_IPC_PANIC_MEM); */
- break;
- }
- idelay(delay_count);
- status = io_reg_read(LSPGISTS);
- }
-
- shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_BYPASS);
-
- return status;
-}
-
-/* boot master core */
-void boot_master_core(void)
-{
- int32_t result;
-
- /* TODO: platform trace should write to HW IPC regs on CNL */
- /* platform_trace_point(TRACE_BOOT_LDR_ENTRY); */
-
- /* init the LPSRAM */
- /* platform_trace_point(TRACE_BOOT_LDR_LPSRAM); */
-
- result = lp_sram_init();
- if (result < 0) {
- /* platform_panic(SOF_IPC_PANIC_MEM); */
- return;
- }
-
- /* parse manifest and copy modules */
- /* platform_trace_point(TRACE_BOOT_LDR_MANIFEST); */
- parse_manifest();
-
- /* now call SOF entry */
- /* platform_trace_point(TRACE_BOOT_LDR_JUMP); */
- __start();
-}
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/memory.h b/soc/xtensa/intel_apl_adsp/include/platform/memory.h
deleted file mode 100644
index 88dba2f..0000000
--- a/soc/xtensa/intel_apl_adsp/include/platform/memory.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/* SPDX-License-Identifier: Apache-2.0
- *
- * Copyright(c) 2016 Intel Corporation. All rights reserved.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __PLATFORM_MEMORY_H__
-#define __PLATFORM_MEMORY_H__
-
-/* Memory banks */
-
-#define NUM_LP_MEMORY_BANKS 2
-
-#define NUM_HP_MEMORY_BANKS 8
-
-#define SRAM_BANK_SIZE (64 * 1024)
-
-#define EBB_BANKS_IN_SEGMENT 32
-
-#define EBB_SEGMENT_SIZE EBB_BANKS_IN_SEGMENT
-
-#define PLATFORM_LPSRAM_EBB_COUNT NUM_LP_MEMORY_BANKS
-
-#define PLATFORM_HPSRAM_EBB_COUNT NUM_HP_MEMORY_BANKS
-
-#define LP_SRAM_SIZE (NUM_LP_MEMORY_BANKS * SRAM_BANK_SIZE)
-
-#define HP_SRAM_SIZE (NUM_HP_MEMORY_BANKS * SRAM_BANK_SIZE)
-
-#define LPSRAM_MASK(ignored) ((1 << PLATFORM_LPSRAM_EBB_COUNT) - 1)
-
-#define HPSRAM_MASK(seg_idx) ((1 << (PLATFORM_HPSRAM_EBB_COUNT \
- - EBB_BANKS_IN_SEGMENT * seg_idx)) - 1)
-
-/* physical DSP addresses */
-
-/* shim */
-#define SHIM_BASE 0x00001000
-#define SHIM_SIZE 0x00000100
-
-/* IPC to the host */
-#define IPC_HOST_BASE 0x00001180
-#define IPC_HOST_SIZE 0x00000020
-
-/* Intra DSP IPC */
-#define IPC_DSP_SIZE 0x00000080
-#define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE)
-
-/* SRAM window for HOST */
-#define HOST_WIN_SIZE 0x00000008
-#define HOST_WIN_BASE(x) (0x00001580 + x * HOST_WIN_SIZE)
-
-#define L2_VECTOR_SIZE 0x1000
-
-/*
- * The HP SRAM Region Apollolake is organised like this :-
- * +--------------------------------------------------------------------------+
- * | Offset | Region | Size |
- * +---------------------+----------------+-----------------------------------+
- * | HP_SRAM_BASE | DMA | HEAP_HP_BUFFER_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_EXCEPT_BASE | Debug data W2 | SRAM_EXCEPT_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
- * +---------------------+----------------+-----------------------------------+
- */
-
-/* HP SRAM */
-
-#define HP_SRAM_BASE 0xBE000000
-#define HP_SRAM_MASK 0xFF000000
-
-/* HP SRAM Heap */
-#define HEAP_HP_BUFFER_BASE HP_SRAM_BASE
-#define HEAP_HP_BUFFER_SIZE 0x8000
-
-#define HEAP_HP_BUFFER_BLOCK_SIZE 0x180
-#define HEAP_HP_BUFFER_COUNT \
- (HEAP_HP_BUFFER_SIZE / HEAP_HP_BUFFER_BLOCK_SIZE)
-
-/* HP SRAM windows */
-
-/* window 3 */
-#define SRAM_TRACE_BASE SRAM_WND_BASE
-#define SRAM_TRACE_SIZE 0x2000
-
-/* window 2 */
-#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE)
-#define SRAM_DEBUG_SIZE 0x800
-
-#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
-#define SRAM_EXCEPT_SIZE 0x800
-
-#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
-#define SRAM_STREAM_SIZE 0x1000
-
-/* window 1 */
-#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_INBOX_SIZE 0x2000
-
-/* window 0 */
-#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define SRAM_SW_REG_SIZE 0x1000
-
-/* SRAM window 0 FW "registers" */
-#define SRAM_REG_ROM_STATUS 0x0
-#define SRAM_REG_FW_STATUS 0x4
-#define SRAM_REG_FW_TRACEP 0x8
-#define SRAM_REG_FW_IPC_RECEIVED_COUNT 0xc
-#define SRAM_REG_FW_IPC_PROCESSED_COUNT 0x10
-#define SRAM_REG_FW_END 0x14
-
-#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
-#define SRAM_OUTBOX_SIZE 0x1000
-
-#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE
-#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE)
-#define HP_SRAM_WIN1_BASE SRAM_INBOX_BASE
-#define HP_SRAM_WIN1_SIZE SRAM_INBOX_SIZE
-#define HP_SRAM_WIN2_BASE SRAM_DEBUG_BASE
-#define HP_SRAM_WIN2_SIZE (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \
- SRAM_STREAM_SIZE)
-#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE
-#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
-
-/* Apollolake HP-SRAM config */
-#define SRAM_ALIAS_OFFSET 0x20000000
-
-#define SRAM_WND_BASE (HEAP_HP_BUFFER_BASE + HEAP_HP_BUFFER_SIZE)
-
-#define HP_SRAM_VECBASE_RESET (HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE)
-#define HP_SRAM_VECBASE_OFFSET 0x0
-
-#define SOF_FW_START (HP_SRAM_VECBASE_RESET + 0x400)
-#define SOF_FW_BASE (SOF_FW_START)
-
-/* max size for all var-size sections (text/rodata/bss) */
-#define SOF_FW_MAX_SIZE (0x41000 - 0x400)
-
-#define SOF_TEXT_START (SOF_FW_START)
-#define SOF_TEXT_BASE (SOF_FW_START)
-
-/* Stack configuration */
-#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
-#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
-
-#define SOF_MEMORY_SIZE (SOF_STACK_BASE - HP_SRAM_BASE)
-
-/* LP SRAM */
-#define LP_SRAM_BASE 0xBE800000
-
-/* boot loader in IMR */
-#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB000A000
-
-#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x86
-
-/* Manifest base address in IMR - used by boot loader copy procedure. */
-#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000
-
-/* Manifest size (seems unused). */
-#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000
-
-#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/shim.h b/soc/xtensa/intel_apl_adsp/include/platform/shim.h
deleted file mode 100644
index 51cb888..0000000
--- a/soc/xtensa/intel_apl_adsp/include/platform/shim.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* SPDX-License-Identifier: Apache-2.0
- *
- * Copyright(c) 2016 Intel Corporation. All rights reserved.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __PLATFORM_SHIM_H__
-#define __PLATFORM_SHIM_H__
-
-#include <platform/memory.h>
-
-#ifndef ASSEMBLY
-#include <stdint.h>
-#endif
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-#include <sys/sys_io.h>
-#include <arch/common/sys_io.h>
-#endif
-
-#ifndef BIT
-#define BIT(b) (1 << (b))
-#endif
-
-/* DSP IPC for Host Registers */
-#define IPC_DIPCT 0x00
-#define IPC_DIPCTE 0x04
-#define IPC_DIPCI 0x08
-#define IPC_DIPCIE 0x0c
-#define IPC_DIPCCTL 0x10
-
-/* DIPCT */
-#define IPC_DIPCT_BUSY (1 << 31)
-#define IPC_DIPCT_MSG_MASK 0x7FFFFFFF
-
-/* DIPCTE */
-#define IPC_DIPCTE_MSG_MASK 0x3FFFFFFF
-
-/* DIPCI */
-#define IPC_DIPCI_BUSY (1 << 31)
-#define IPC_DIPCI_MSG_MASK 0x7FFFFFFF
-
-/* DIPCIE */
-#define IPC_DIPCIE_DONE (1 << 30)
-#define IPC_DIPCIE_MSG_MASK 0x3FFFFFFF
-
-/* DIPCCTL */
-#define IPC_DIPCCTL_IPCIDIE (1 << 1)
-#define IPC_DIPCCTL_IPCTBIE (1 << 0)
-
-#define IPC_DSP_OFFSET 0x10
-
-#define SHIM_PWRCTL 0x90
-#define SHIM_PWRSTS 0x92
-#define SHIM_LPSCTL 0x94
-
-/* HP & LP SRAM Power Gating */
-#define SHIM_HSPGCTL 0x80
-#define SHIM_LSPGCTL 0x84
-#define SHIM_SPSREQ 0xa0
-#define LSPGCTL SHIM_LSPGCTL
-
-#define SHIM_SPSREQ_RVNNP (0x1 << 0)
-
-/** \brief LDO Control */
-#define SHIM_LDOCTL 0xA4
-#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0)
-#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
-#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
-#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
-#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
-#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
-#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
-#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
-
-#define SHIM_HSPGISTS 0xb0
-#define SHIM_LSPGISTS 0xb4
-#define LSPGISTS (SHIM_BASE + SHIM_LSPGISTS)
-
-
-#define SHIM_LPSCTL_FDSPRUN (0X1 << 9)
-#define SHIM_LPSCTL_FDMARUN (0X1 << 8)
-
-#define SHIM_L2_MECS (SHIM_BASE + 0xd0)
-
-#define SHIM_L2_CACHE_CTRL (SHIM_BASE + 0x500)
-#define SHIM_L2_PREF_CFG (SHIM_BASE + 0x508)
-#define SHIM_L2_CACHE_PREF (SHIM_BASE + 0x510)
-
-/* host windows */
-#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0)
-#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4)
-
-#define DMWBA_ENABLE (1 << 0)
-#define DMWBA_READONLY (1 << 1)
-
-#if !defined(__ASSEMBLER__) && !defined(LINKER)
-
-static inline uint32_t shim_read(uint32_t reg)
-{
- return sys_read32(SHIM_BASE + reg);
-}
-
-static inline void shim_write(uint32_t reg, uint32_t val)
-{
- sys_write32(val, (SHIM_BASE + reg));
-}
-
-static inline uint32_t ipc_read(uint32_t reg)
-{
- return sys_read32(IPC_HOST_BASE + reg);
-}
-
-static inline void ipc_write(uint32_t reg, uint32_t val)
-{
- sys_write32(val, (IPC_HOST_BASE + reg));
-}
-
-#endif /* !defined(__ASSEMBLER__) && !defined(LINKER) */
-
-#endif
diff --git a/soc/xtensa/intel_apl_adsp/memory.h b/soc/xtensa/intel_apl_adsp/memory.h
deleted file mode 100644
index 2d526bd..0000000
--- a/soc/xtensa/intel_apl_adsp/memory.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (c) 2019 Intel Corporation
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __INC_MEMORY_H
-#define __INC_MEMORY_H
-
-/* L2 HP SRAM */
-#define HP_RAM_RESERVE_HEADER_SPACE 0x00010000
-
-#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
-#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
-
-#ifdef CONFIG_BOOTLOADER_MCUBOOT
-#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
-#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
-#else
-#define SRAM_BASE (L2_SRAM_BASE)
-#define SRAM_SIZE (L2_SRAM_SIZE)
-#endif
-
-/* The reset vector address in SRAM and its size */
-#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE
-#define MEM_RESET_TEXT_SIZE 0x268
-#define MEM_RESET_LIT_SIZE 0x8
-
-/* This is the base address of all the vectors defined in SRAM */
-#define XCHAL_VECBASE_RESET_PADDR_SRAM \
- (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE)
-
-#define MEM_VECBASE_LIT_SIZE 0x178
-
-/* The addresses of the vectors in SRAM.
- * Only the memerror vector continues to point to its ROM address.
- */
-#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM \
- (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x180)
-
-#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM \
- (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x1C0)
-
-#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM \
- (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x200)
-
-#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM \
- (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x240)
-
-#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM \
- (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x280)
-
-#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM \
- (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x2C0)
-
-#define XCHAL_KERNEL_VECTOR_PADDR_SRAM \
- (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x300)
-
-#define XCHAL_USER_VECTOR_PADDR_SRAM \
- (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x340)
-
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM \
- (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x3C0)
-
-#define VECTOR_TBL_SIZE 0x0400
-
-/* Vector and literal sizes */
-#define MEM_VECT_LIT_SIZE 0x8
-#define MEM_VECT_TEXT_SIZE 0x38
-#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
- MEM_VECT_LIT_SIZE)
-
-/* The memerror vector address is copied as is from core-isa.h */
-#define XCHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400
-
-#define MEM_ERROR_TEXT_SIZE 0x180
-#define MEM_ERROR_LIT_SIZE 0x8
-
-/* text and data share the same L2 HP SRAM.
- * So, they lie next to each other.
- */
-#define RAM_BASE \
- (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE + VECTOR_TBL_SIZE)
-
-#define RAM_SIZE \
- (SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
-
-/* Location for the intList section which is later used to construct the
- * Interrupt Descriptor Table (IDT). This is a bogus address as this
- * section will be stripped off in the final image.
- */
-#define IDT_BASE (RAM_BASE + RAM_SIZE)
-
-/* size of the Interrupt Descriptor Table (IDT) */
-#define IDT_SIZE 0x2000
-
-/* low power ram where DMA buffers are typically placed */
-#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
-#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
-
-#include <platform/memory.h>
-
-#endif /* __INC_MEMORY_H */
diff --git a/subsys/logging/Kconfig b/subsys/logging/Kconfig
index 63c0354..fd1596d 100644
--- a/subsys/logging/Kconfig
+++ b/subsys/logging/Kconfig
@@ -452,7 +452,7 @@
config LOG_BACKEND_XTENSA_SIM
bool "Enable xtensa simulator backend"
- depends on SOC_XTENSA_SAMPLE_CONTROLLER || SOC_INTEL_APL_ADSP
+ depends on SOC_XTENSA_SAMPLE_CONTROLLER || SOC_FAMILY_INTEL_ADSP
help
Enable backend in xtensa simulator
