| commit | dadf9e7a81de66e2578fe85c2d66cc3d284225f4 | [log] [tgz] |
|---|---|---|
| author | Rajavardhan Gundi <rajavardhan.gundi@intel.com> | Thu Oct 12 18:32:23 2017 +0530 |
| committer | Anas Nashif <nashif@linux.intel.com> | Tue May 01 16:46:41 2018 -0400 |
| tree | 81af318d9ffcc347e91e2fe9dba60e5f21062890 | |
| parent | e3f2fa4f8966dcbd6a57b37d340592d6e2614bd3 [diff] |
xtensa: intel_s1000: implement interrupt mechanism intel_s1000 has multiple levels of interrupts consisting of core, CAVS Logic and designware interrupt controller. This patchset modifies the regular gen_isr mechanism to support these multiple levels. Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>