58d50a0e979b49d431e5a144b30787681d7a5cc7 - third_party/github/zephyrproject-rtos/zephyr

commit	58d50a0e979b49d431e5a144b30787681d7a5cc7	[log] [tgz]
author	Henry Hsieh <r901042004@yahoo.com.tw>	Tue Dec 14 22:46:42 2021 +0800
committer	Carles Cufí <carles.cufi@nordicsemi.no>	Fri Feb 04 11:23:39 2022 +0100
tree	7616990e4ddd3d573ccd8bee927a6a3f6b72ce79
parent	9edb8e2afb3b04d2d34194c59ac0f9b4a86327fa [diff]

riscv: fix non-standard assembly of RISC-V

Non-standard `jalr rd, rs` pseudo-instructions are used.
This commit changes them to `ret` for standard return pseudo-instruction
or `jalr rd, rs, 0` for no offset jump register and link.

Fixes #41100.

Signed-off-by: Henry Hsieh <r901042004@yahoo.com.tw>

arch/riscv/core/isr.S[diff]
arch/riscv/core/swap.S[diff]
soc/riscv/esp32c3/soc_irq.S[diff]
soc/riscv/riscv-ite/common/soc_irq.S[diff]
soc/riscv/riscv-privilege/common/soc_irq.S[diff]
soc/riscv/riscv-privilege/neorv32/soc_irq.S[diff]

6 files changed