| commit | 596e44d244cdb9dc317a9e7193bfbb6d459eed7b | [log] [tgz] |
|---|---|---|
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | Wed Nov 21 11:30:29 2018 -0800 |
| committer | Kumar Gala <kumar.gala@gmail.com> | Wed Feb 06 09:00:00 2019 -0600 |
| tree | 70f698364339544ff911d21b96995f5abdf0560b | |
| parent | 9e2ef8db6d74bc9d7df14fafa866fef771001c3b [diff] |
soc/riscv32-fe310: Enable DTS gen for SPI Add the SPI bus DTS generation to the FE310 and the SiFive Freedom SoC. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>