| commit | 80a863f9470d44ee6760f0b3e059d7b4a648865e | [log] [tgz] |
|---|---|---|
| author | Mahesh Rao <mahesh.rao@intel.com> | Thu Jun 22 06:00:14 2023 +0000 |
| committer | Carles Cufí <carles.cufi@nordicsemi.no> | Fri Sep 15 09:26:49 2023 +0200 |
| tree | 8824d879a596eb2b1049335998a767358f2792db | |
| parent | 1a4e5dff5d32960076b1a3c6b37bee0354821197 [diff] |
tests: sip_svc: Add a stress test for sip_svc subsystem Add a stress test for sip_svc subsystem using INTEL SOCFPGA AGILEX platform. Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>