commit | 5d8a9206b8f8434fdac0d6e0ab29cfcc1cedd633 | [log] [tgz] |
---|---|---|
author | Krishna Mohan Dani <krishnamohan.d@hcl.com> | Wed Jun 16 12:58:30 2021 +0530 |
committer | Carles CufĂ <carles.cufi@nordicsemi.no> | Thu Jun 17 12:40:39 2021 +0200 |
tree | 01946846d752c013aa9bf2ee75efbea3be12f18c | |
parent | 27435cf6e50e750c30542c74282d19fb14ab226d [diff] |
soc: arm: stm32f2: enable ART flash cache accelerator This commit enables Instruction cache and Data cache. Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>