| commit | 5dfd3c3786a3c8d03d215a33ea6023d9a093d2e7 | [log] [tgz] |
|---|---|---|
| author | Daniel DeGrasse <daniel.degrasse@nxp.com> | Tue Feb 01 19:33:18 2022 -0600 |
| committer | Carles Cufí <carles.cufi@nordicsemi.no> | Wed Feb 02 16:59:30 2022 +0100 |
| tree | a22e523f93d0521f3d44829600dd4a4aec813ba4 | |
| parent | 2355fe86da1b0cdd1e4df97ab936ca4633deea83 [diff] |
soc: rt10xx: Set divisor for sys pll (PLL2) PFD0 Divisor must be set to calculate SD host controller clock frequency in clock driver. Fixes #42380 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>