commit 5f70091dbb13b7755ee528cfa7e45b700e678f2e
author Andy Ross <andyross@google.com> Wed Aug 10 11:37:23 2022 -0700
committer Carles Cufí <carles.cufi@nordicsemi.no> Thu Aug 18 10:19:19 2022 +0200
tree 12b5f1ab9856173b9877d5f2473af315b82a2cfc
parent e05d0132fd98b5bb805f7e0910b9a82c384f5936

boards/qemu_cortex_a53: enable qemu icount mode

This is a single-CPU board that would normally be expected to have
icount enabled, but doesn't.  So it sees a ton of false positive test
failures due to timing skew, which (for still-poorly-understood
reasons) have recently become much worse in CI.

It looks like this got held back by a qemu bug where the emulator
would ignore SIGTERM, but that can be worked around in twister.

Turn it on.  The SHIFT value of 4 matches the 62.5 MHz simulated
clock exactly, which is pleasing.

Signed-off-by: Andy Ross <andyross@google.com>

boards/arm64/qemu_cortex_a53/qemu_cortex_a53_defconfig

diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_defconfig b/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_defconfig
index c3f19da..4c19444 100644
--- a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_defconfig
+++ b/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_defconfig
@@ -1,7 +1,9 @@
 CONFIG_SOC_QEMU_CORTEX_A53=y
 CONFIG_BOARD_QEMU_CORTEX_A53=y
 CONFIG_ARM_ARCH_TIMER=y
-CONFIG_QEMU_ICOUNT=n
+CONFIG_QEMU_ICOUNT=y
+CONFIG_QEMU_ICOUNT_SHIFT=4
+CONFIG_QEMU_ICOUNT_SLEEP=y
 
 # Cache management
 CONFIG_CACHE_MANAGEMENT=y