| commit | b5016714b08273da6eba7a0a115ee2a2e22cc24f | [log] [tgz] |
|---|---|---|
| author | Daniel Leung <daniel.leung@intel.com> | Thu Aug 17 15:36:47 2023 -0700 |
| committer | Anas Nashif <anas.nashif@intel.com> | Sat Aug 26 16:50:40 2023 -0400 |
| tree | d87f8f3e51283080b926d5c29017e7086a4f4b20 | |
| parent | 98ffd1addd6a606d07a916b8ab1a6b9b63c068da [diff] |
xtensa: mmu: handle TLB misses during user exception This adds code to deal with TLB misses as these comes as level 1 interrupts. Signed-off-by: Daniel Leung <daniel.leung@intel.com>