| commit | 62a30eba8696629fb61f23a62575b710008f3f50 | [log] [tgz] |
|---|---|---|
| author | Jim Shu <cwshu@andestech.com> | Thu Jul 29 10:48:41 2021 +0800 |
| committer | Anas Nashif <anas.nashif@intel.com> | Mon Aug 30 13:40:14 2021 -0400 |
| tree | 35a1a8e1bc8ac5c06941a1c52ebbef3b0415f8ec | |
| parent | 0f3d2d923072feeeab1104d3c9d1fe2a2dbda496 [diff] |
soc: riscv: add initial support of andes_v5 soc series Add andes_v5 SoC series and andes_ae350 SoC. It includes soc initialization code, linker script, and custom CSR encoding. Signed-off-by: Jim Shu <cwshu@andestech.com>