soc: silabs: Support devices with 3 PPU registers
Support xg26, which has a third PPU security attribution register.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
diff --git a/soc/silabs/silabs_s2/soc.c b/soc/silabs/silabs_s2/soc.c
index f9af455..bfdfc08 100644
--- a/soc/silabs/silabs_s2/soc.c
+++ b/soc/silabs/silabs_s2/soc.c
@@ -92,11 +92,16 @@
CMU_S->CLKEN1_SET = CMU_CLKEN1_SMU;
#endif
SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK;
-#if defined(SEMAILBOX_PRESENT)
+#if defined(SEMAILBOX_PRESENT) && defined(SMU_PPUSATD1_SEMAILBOX)
SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & (~SMU_PPUSATD1_SMU & ~SMU_PPUSATD1_SEMAILBOX));
#else
SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & ~SMU_PPUSATD1_SMU);
#endif
+#if defined(SEMAILBOX_PRESENT) && defined(SMU_PPUSATD2_SEMAILBOX)
+ SMU->PPUSATD2_CLR = (_SMU_PPUSATD2_MASK & ~SMU_PPUSATD2_SEMAILBOX);
+#elif defined(_SMU_PPUSATD2_MASK)
+ SMU->PPUSATD2_CLR = _SMU_PPUSATD2_MASK;
+#endif
SAU->CTRL = SAU_CTRL_ALLNS_Msk;
__DSB();
