boards: arm: add nucleo_wl55jc board support
Add support of nucleo_wl55jc board
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
diff --git a/boards/arm/nucleo_wl55jc/Kconfig.board b/boards/arm/nucleo_wl55jc/Kconfig.board
new file mode 100644
index 0000000..ece57d5
--- /dev/null
+++ b/boards/arm/nucleo_wl55jc/Kconfig.board
@@ -0,0 +1,8 @@
+# STM32WL55JC Nucleo board configuration
+
+# Copyright (c) 2020 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NUCLEO_WL55JC
+ bool "Nucleo WL55JC Development Board"
+ depends on SOC_STM32WL55XX
diff --git a/boards/arm/nucleo_wl55jc/Kconfig.defconfig b/boards/arm/nucleo_wl55jc/Kconfig.defconfig
new file mode 100644
index 0000000..981e20f
--- /dev/null
+++ b/boards/arm/nucleo_wl55jc/Kconfig.defconfig
@@ -0,0 +1,11 @@
+# STM32WL55JC Nucleo board configuration
+
+# Copyright (c) 2020 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NUCLEO_WL55JC
+
+config BOARD
+ default "nucleo_wl55jc"
+
+endif # BOARD_NUCLEO_WL55JC
diff --git a/boards/arm/nucleo_wl55jc/arduino_r3_connector.dtsi b/boards/arm/nucleo_wl55jc/arduino_r3_connector.dtsi
new file mode 100644
index 0000000..1e9779c
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+++ b/boards/arm/nucleo_wl55jc/arduino_r3_connector.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+ arduino_header: connector {
+ compatible = "arduino-header-r3";
+ #gpio-cells = <2>;
+ gpio-map-mask = <0xffffffff 0xffffffc0>;
+ gpio-map-pass-thru = <0 0x3f>;
+ gpio-map = <0 0 &gpiob 1 0>, /* A0 */
+ <1 0 &gpiob 2 0>, /* A1 */
+ <2 0 &gpioa 10 0>, /* A2 */
+ <3 0 &gpiob 4 0>, /* A3 */
+ <4 0 &gpiob 14 0>, /* A4 */
+ <5 0 &gpiob 13 0>, /* A5 */
+ <6 0 &gpiob 7 0>, /* D0 */
+ <7 0 &gpiob 6 0>, /* D1 */
+ <8 0 &gpiob 12 0>, /* D2 */
+ <9 0 &gpiob 3 0>, /* D3 */
+ <10 0 &gpiob 5 0>, /* D4 */
+ <11 0 &gpiob 8 0>, /* D5 */
+ <12 0 &gpiob 10 0>, /* D6 */
+ <13 0 &gpioc 1 0>, /* D7 */
+ <14 0 &gpioc 2 0>, /* D8 */
+ <15 0 &gpioa 9 0>, /* D9 */
+ <16 0 &gpioa 4 0>, /* D10 */
+ <17 0 &gpioa 7 0>, /* D11 */
+ <18 0 &gpioa 6 0>, /* D12 */
+ <19 0 &gpioa 5 0>, /* D13 */
+ <20 0 &gpiob 11 0>, /* D14 */
+ <21 0 &gpiob 12 0>; /* D15 */
+ };
+};
+
+arduino_serial: &lpuart1 {};
diff --git a/boards/arm/nucleo_wl55jc/board.cmake b/boards/arm/nucleo_wl55jc/board.cmake
new file mode 100644
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+++ b/boards/arm/nucleo_wl55jc/board.cmake
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset=hw")
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
\ No newline at end of file
diff --git a/boards/arm/nucleo_wl55jc/doc/img/nucleo_wl55jc.jpg b/boards/arm/nucleo_wl55jc/doc/img/nucleo_wl55jc.jpg
new file mode 100644
index 0000000..539ffc3
--- /dev/null
+++ b/boards/arm/nucleo_wl55jc/doc/img/nucleo_wl55jc.jpg
Binary files differ
diff --git a/boards/arm/nucleo_wl55jc/doc/nucleo_wl55jc.rst b/boards/arm/nucleo_wl55jc/doc/nucleo_wl55jc.rst
new file mode 100644
index 0000000..4017a22
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+++ b/boards/arm/nucleo_wl55jc/doc/nucleo_wl55jc.rst
@@ -0,0 +1,290 @@
+.. _nucleo_wl55jc_board:
+
+ST Nucleo WL55JC
+################
+
+Overview
+********
+
+The NUCLEO-WL55JC STM32WL Nucleo-64 board provides an affordable and flexible
+way for users to try out new concepts and build prototypes with the STM32WL
+Series microcontroller, choosing from the various combinations of performance,
+power consumption, and features.
+
+- STM32WL55JC microcontroller multiprotocol LPWAN dual-core 32-bit
+ (Arm® Cortex®-M4/M0+ at 48 MHz) in UFBGA73 package featuring:
+
+ - Ultra-low-power MCU
+ - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®,
+ (G)FSK, (G)MSK, and BPSK modulations
+ - 256-Kbyte Flash memory and 64-Kbyte SRAM
+
+- 3 user LEDs
+- 3 user buttons and 1 reset push-button
+- 32.768 kHz LSE crystal oscillator
+- 32 MHz HSE on-board oscillator
+- Board connectors:
+
+ - USB with Micro-B
+ - MIPI debug connector
+ - ARDUINO Uno V3 expansion connector
+ - ST morpho extension pin headers for full access to all STM32WL I/Os
+
+- Delivered with SMA antenna
+- Flexible power-supply options: ST-LINK, USB VBUS, or external sources
+- On-board STLINK-V3 debugger/programmer with USB re-enumeration capability:
+ mass storage, Virtual COM port, and debug port
+- Comprehensive free software libraries and examples available with the
+ STM32CubeWL MCU Package
+- Support of a wide choice of Integrated Development Environments (IDEs)
+ including IAR Embedded Workbench®, MDK-ARM, and STM32CubeIDE
+- Suitable for rapid prototyping of end nodes based on LoRaWAN, Sigfox, wM-Bus,
+ and many other proprietary protocols
+- Fully open hardware platform
+
+
+.. image:: img/nucleo_wl55jc.jpg
+ :width: 426px
+ :align: center
+ :height: 683px
+ :alt: Nucleo WL55JC
+
+More information about the board can be found at the `Nucleo WL55JC website`_.
+
+Hardware
+********
+
+The STM32WL55JC long-range wireless and ultra-low-power devices embed a powerful
+and ultra-low-power LPWAN-compliant radio solution, enabling the following
+modulations: LoRa®, (G)FSK, (G)MSK, and BPSK
+It provides the following hardware capabilities:
+
+- Radio
+
+ - Frequency range: 150 MHz to 960 MHz
+ - Modulation: LoRa®, (G)FSK, (G)MSK and BPSK
+ - RX sensitivity: –123 dBm for 2-FSK(at 1.2 Kbit/s), –148 dBm for LoRa®
+ (at 10.4 kHz, spreading factor 12)
+ - Transmitter high output power, programmable up to +22 dBm
+ - Transmitter low output power, programmable up to +15 dBm
+ - Compliant with the following radio frequency regulations such as
+ ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 Part 15, 24, 90, 101
+ and the Japanese ARIB STD-T30, T-67, T-108
+ - Compatible with standardized or proprietary protocols such as LoRaWAN®,
+ Sigfox™, W-MBus and more (fully open wireless system-on-chip)
+
+- Core
+
+ - 32-bit Arm® Cortex®-M4 CPU
+
+ - Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state
+ execution from Flash memory, frequency up to 48 MHz, MPU
+ and DSP instructions
+ - 1.25 DMIPS/MHz (Dhrystone 2.1)
+
+ - 32-bit Arm®Cortex®-M0+ CPU
+
+ - Frequency up to 48 MHz, MPU
+ - 0.95 DMIPS/MHz (Dhrystone 2.1)
+
+- Security and identification
+
+ - Hardware encryption AES 256-bit
+ - True random number generator (RNG)
+ - Sector protection against read/write operations (PCROP, RDP, WRP)
+ - CRC calculation unit
+ - Unique device identifier (64-bit UID compliant with IEEE 802-2001 standard)
+ - 96-bit unique die identifier
+ - Hardware public key accelerator (PKA)
+ - Key management services
+ - Secure sub-GHz MAC layer
+ - Secure firmware update (SFU)
+ - Secure firmware install (SFI)
+
+- Supply and reset management
+
+ - High-efficiency embedded SMPS step-down converter
+ - SMPS to LDO smart switch
+ - Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds
+ - Ultra-low-power POR/PDR
+ - Programmable voltage detector (PVD)
+ - VBAT mode with RTC and 20x32-byte backup registers
+
+- Clock sources
+
+ - 32 MHz crystal oscillator
+ - TCXO support: programmable supply voltage
+ - 32 kHz oscillator for RTC with calibration
+ - High-speed internal 16 MHz factory trimmed RC (± 1 %)
+ - Internal low-power 32 kHz RC
+ - Internal multi-speed low-power 100 kHz to 48 MHz RC
+ - PLL for CPU, ADC and audio clocks
+
+- Memories
+
+ - 256-Kbyte Flash memory
+ - 64-Kbyte RAM
+ - 20x32-bit backup register
+ - Bootloader supporting USART and SPI interfaces
+ - OTA (over-the-air) firmware update capable
+ - Sector protection against read/write operations
+
+- Rich analog peripherals (down to 1.62 V)
+
+ - 12-bit ADC 2.5 Msps, up to 16 bits with hardware oversampling,
+ conversion range up to 3.6 V
+ - 12-bit DAC, low-power sample-and-hold
+ - 2x ultra-low-power comparators
+
+- System peripherals
+
+ - Mailbox and semaphores for communication between Cortex®-M4 and Cortex®-M0+
+ firmware
+
+- Controllers
+
+ - 2x DMA controller (7 channels each) supporting ADC, DAC, SPI, I2C, LPUART,
+ USART, AES and timers
+ - 2x USART (ISO 7816, IrDA, SPI)
+ - 1x LPUART (low-power)
+ - 2x SPI 16 Mbit/s (1 over 2 supporting I2S)
+ - 3x I2C (SMBus/PMBus™)
+ - 2x 16-bit 1-channel timer
+ - 1x 16-bit 4-channel timer (supporting motor control)
+ - 1x 32-bit 4-channel timer
+ - 3x 16-bit ultra-low-power timer
+ - 1x RTC with 32-bit sub-second wakeup counter
+ - 1x independent SysTick
+ - 1x independent watchdog
+ - 1x window watchdog
+
+- Up to 43 I/Os, most 5 V-tolerant
+- Development support
+ - Serial-wire debug (SWD), JTAG
+ - Dual CPU cross trigger capabilities
+
+
+More information about STM32WL55JC can be found here:
+
+- `STM32WL55JC on www.st.com`_
+- `STM32WL55JC datasheet`_
+- `STM32WL55JC reference manual`_
+
+Supported Features
+==================
+
+The Zephyr nucleo_wl55jc board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component |
++===========+============+=====================================+
+| NVIC | on-chip | nested vector interrupt controller |
++-----------+------------+-------------------------------------+
+| UART | on-chip | serial port-polling; |
+| | | serial port-interrupt |
++-----------+------------+-------------------------------------+
+| PINMUX | on-chip | pinmux |
++-----------+------------+-------------------------------------+
+| GPIO | on-chip | gpio |
++-----------+------------+-------------------------------------+
+
+
+Other hardware features are not yet supported on this Zephyr port.
+
+The default configuration can be found in the defconfig file:
+``boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig``
+
+
+Connections and IOs
+===================
+
+Nucleo WL55JC Board has 4 GPIO controllers. These controllers are responsible
+for pin muxing, input/output, pull-up, etc.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+.. rst-class:: rst-columns
+
+- LPUART_1 TX/RX : PA3/PA2 (ST-Link Virtual Port Com)
+
+System Clock
+------------
+
+Nucleo WL55JC System Clock could be driven by internal or external oscillator,
+as well as main PLL clock. By default System clock is driven by HSE clock at
+32MHz.
+
+Serial Port
+-----------
+
+Nucleo WL55JC board has 2 (LP)U(S)ARTs. The Zephyr console output is assigned
+to LPUART_1.
+Default settings are 115200 8N1.
+
+
+Programming and Debugging
+*************************
+
+Applications for the ``nucleo_wl55jc`` board configuration can be built the
+usual way (see :ref:`build_an_application`).
+
+Flashing
+========
+
+Nucleo WL55JC board includes an STLINK-V3 embedded debug tool
+interface. This interface is supported by the openocd version included in the
+Zephyr SDK since v0.11.0.
+You can also choose the ``stm32cubeprogrammer`` runner.
+
+
+Flashing an application to Nucleo WL55JC
+----------------------------------------
+
+Connect the Nucleo WL55JC to your host computer using the USB port.
+Then build and flash an application. Here is an example for the
+:ref:`hello_world` application.
+
+Run a serial host program to connect with your Nucleo board:
+
+.. code-block:: console
+
+ $ minicom -D /dev/ttyUSB0
+
+Then build and flash the application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: nucleo_wl55jc
+ :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+ Hello World! arm
+
+Debugging
+=========
+
+You can debug an application in the usual way. Here is an example for the
+:ref:`blinky-sample` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/basic/blinky
+ :board: nucleo_wl55jc
+ :maybe-skip-config:
+ :goals: debug
+
+.. _Nucleo WL55JC website:
+ https://www.st.com/en/evaluation-tools/nucleo-wl55jc.html
+
+.. _STM32WL55JC on www.st.com:
+ https://www.st.com/en/microcontrollers-microprocessors/stm32wl55jc.html
+
+.. _STM32WL55JC datasheet:
+ https://www.st.com/resource/en/datasheet/stm32wl55jc.pdf
+
+.. _STM32WL55JC reference manual:
+ https://www.st.com/resource/en/reference_manual/dm00451556-stm32wl5x-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf
diff --git a/boards/arm/nucleo_wl55jc/nucleo_wl55jc.dts b/boards/arm/nucleo_wl55jc/nucleo_wl55jc.dts
new file mode 100644
index 0000000..293dc46
--- /dev/null
+++ b/boards/arm/nucleo_wl55jc/nucleo_wl55jc.dts
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2020 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/wl/stm32wl55Xc.dtsi>
+#include <st/wl/stm32wl55jcix-pinctrl.dtsi>
+#include "arduino_r3_connector.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32WL55JC-NUCLEO board";
+ compatible = "st,stm32wl55-nucleo";
+
+ chosen {
+ zephyr,console = &lpuart1;
+ zephyr,shell-uart = &lpuart1;
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash0;
+ zephyr,code-partition = &flash0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ blue_led_1: led_0 {
+ gpios = <&gpiob 15 GPIO_ACTIVE_HIGH>;
+ label = "User LED1";
+ };
+ green_led_2: led_1 {
+ gpios = <&gpiob 9 GPIO_ACTIVE_HIGH>;
+ label = "User LED2";
+ };
+ green_led_3: led_2 {
+ gpios = <&gpiob 11 GPIO_ACTIVE_HIGH>;
+ label = "User LED3";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ user_button_1: button_0 {
+ label = "SW1";
+ gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+ user_button_2: button_1 {
+ label = "SW2";
+ gpios = <&gpioa 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+ user_button_3: button_2 {
+ label = "SW3";
+ gpios = <&gpioc 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+ };
+
+ aliases {
+ led0 = &green_led_2;
+ sw0 = &user_button_1;
+ sw1 = &user_button_2;
+ sw2 = &user_button_3;
+ };
+};
+
+&lpuart1 {
+ pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
+ current-speed = <115200>;
+ status = "okay";
+};
+
+
+&flash0 {
+ /*
+ * For more information, see:
+ * http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions
+ */
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Set 2Kb of storage at the end of the 256Kb of flash */
+ storage_partition: partition@3f800 {
+ label = "storage";
+ reg = <0x0003f800 0x00000800>;
+ };
+ };
+};
diff --git a/boards/arm/nucleo_wl55jc/nucleo_wl55jc.yaml b/boards/arm/nucleo_wl55jc/nucleo_wl55jc.yaml
new file mode 100644
index 0000000..3105e36
--- /dev/null
+++ b/boards/arm/nucleo_wl55jc/nucleo_wl55jc.yaml
@@ -0,0 +1,13 @@
+identifier: nucleo_wl55jc
+name: ST Nucleo WL55JC
+type: mcu
+arch: arm
+toolchain:
+ - zephyr
+ - gnuarmemb
+ - xtools
+ram: 64
+flash: 256
+supported:
+ - gpio
+ - arduino_gpio
diff --git a/boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig b/boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig
new file mode 100644
index 0000000..cec58f3
--- /dev/null
+++ b/boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig
@@ -0,0 +1,43 @@
+CONFIG_SOC_SERIES_STM32WLX=y
+CONFIG_SOC_STM32WL55XX=y
+# 48MHz system clock
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
+
+# enable uart driver
+CONFIG_SERIAL=y
+
+# enable pinmux
+CONFIG_PINMUX=y
+
+# enable GPIO
+CONFIG_GPIO=y
+
+# clock configuration
+CONFIG_CLOCK_CONTROL=y
+# SYSCLK selection
+CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
+# use HSI as PLL input
+CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
+
+# HSE is present on nucleo board (32MHz), but reserved for further LoRa use
+# CONFIG_CLOCK_STM32_HSE_CLOCK=32000000
+
+# produce 80MHz clock at PLL output
+CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
+CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=6
+CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
+CONFIG_CLOCK_STM32_CPU1_PRESCALER=1
+CONFIG_CLOCK_STM32_CPU2_PRESCALER=1
+CONFIG_CLOCK_STM32_APB1_PRESCALER=1
+CONFIG_CLOCK_STM32_APB2_PRESCALER=1
+CONFIG_CLOCK_STM32_AHB3_PRESCALER=1
+
+# console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
diff --git a/boards/arm/nucleo_wl55jc/support/openocd.cfg b/boards/arm/nucleo_wl55jc/support/openocd.cfg
new file mode 100644
index 0000000..f490269
--- /dev/null
+++ b/boards/arm/nucleo_wl55jc/support/openocd.cfg
@@ -0,0 +1,7 @@
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+source [find target/stm32wlx.cfg]
+
+reset_config srst_only
