68799d507da32fde0459c6abffba33182ba73f2f - third_party/github/zephyrproject-rtos/zephyr

commit	68799d507da32fde0459c6abffba33182ba73f2f	[log] [tgz]
author	Gerard Marull-Paretas <gerard@teslabs.com>	Tue Jan 16 16:31:26 2024 +0100
committer	Carles Cufí <carles.cufi@nordicsemi.no>	Tue Jan 23 09:57:57 2024 +0100
tree	45f90ced187ed229288ad7501d710beadac2b3d2
parent	49e2bc69a2fc5a8cbb2873d4a35fd416a38ee84d [diff]

arch: riscv: make __soc_is_irq optional

It looks like all SoCs in tree check if an exception comes from an IRQ
the same way, so let's provide a common logic by default, still
customizable if the SoC selects RISCV_SOC_ISR_CHECK.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>

arch/riscv/Kconfig[diff]
arch/riscv/core/isr.S[diff]
include/zephyr/arch/riscv/irq.h[diff]
soc/riscv/common/riscv-privileged/soc_irq.S[diff]
soc/riscv/espressif_esp32/esp32c3/soc_irq.S[diff]
soc/riscv/ite_ec/common/soc_irq.S[diff]
soc/riscv/openisa_rv32m1/soc_irq.S[diff]

7 files changed