drivers: spi_xlnx_axi_quadspi: Optimize FIFO handling
Add an optional DT property to specify the size of the RX/TX FIFO
implemented within the SPI core. The property name used is the same one
used by Xilinx's device tree generator.
When the FIFO is known to exist, we can use the RX FIFO occupancy register
to determine how many words can be read from the RX FIFO without checking
the RX FIFO empty flag after every read. Likewise with the TX FIFO, we can
use the FIFO size to avoid checking the FIFO full flag after every write.
This can increase overall throughput.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
2 files changed
