| commit | 6a12fb20ab0a8df2c4d4279b3eee59c69b5a7005 | [log] [tgz] |
|---|---|---|
| author | Remy Luisant <remy@luisant.ca> | Fri Nov 19 11:54:50 2021 -0800 |
| committer | Anas Nashif <anas.nashif@intel.com> | Wed Jan 19 13:48:21 2022 -0500 |
| tree | 6ab16ddcf95c836e9ed75daa69234317a793854b | |
| parent | 9175ed8244d357f156da2cd161535eee3e9e0836 [diff] |
timer: Add tickless support for the MIPS CP0 timer This commit adds support for tickless operation on the MIPS CP0 timer. The code closely follows the Xtensa and RISCV timer drivers. All tests pass. Signed-off-by: Remy Luisant <remy@luisant.ca> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>