drivers/pcie: Move PCIE code to relevant place
Though it was noted that pcie_get_cap() is only used by MSI code so far,
there is no need to put it in msi code. If unused, linker will nuke it.
So let's move things to where it belongs to.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
diff --git a/drivers/pcie/host/msi.c b/drivers/pcie/host/msi.c
index 4b45c35..33721e7 100644
--- a/drivers/pcie/host/msi.c
+++ b/drivers/pcie/host/msi.c
@@ -10,30 +10,6 @@
/* functions documented in include/drivers/pcie/msi.h */
-uint32_t pcie_get_cap(pcie_bdf_t bdf, uint32_t cap_id)
-{
- uint32_t reg = 0U;
- uint32_t data;
-
- data = pcie_conf_read(bdf, PCIE_CONF_CMDSTAT);
- if (data & PCIE_CONF_CMDSTAT_CAPS) {
- data = pcie_conf_read(bdf, PCIE_CONF_CAPPTR);
- reg = PCIE_CONF_CAPPTR_FIRST(data);
- }
-
- while (reg) {
- data = pcie_conf_read(bdf, reg);
-
- if (PCIE_CONF_CAP_ID(data) == cap_id) {
- break;
- }
-
- reg = PCIE_CONF_CAP_NEXT(data);
- }
-
- return reg;
-}
-
bool pcie_set_msi(pcie_bdf_t bdf, unsigned int irq)
{
bool success = false; /* keepin' the MISRA peeps employed */
diff --git a/drivers/pcie/host/pcie.c b/drivers/pcie/host/pcie.c
index 7a8ebf1..3b18aea 100644
--- a/drivers/pcie/host/pcie.c
+++ b/drivers/pcie/host/pcie.c
@@ -47,6 +47,30 @@
pcie_conf_write(bdf, PCIE_CONF_CMDSTAT, cmdstat);
}
+uint32_t pcie_get_cap(pcie_bdf_t bdf, uint32_t cap_id)
+{
+ uint32_t reg = 0U;
+ uint32_t data;
+
+ data = pcie_conf_read(bdf, PCIE_CONF_CMDSTAT);
+ if (data & PCIE_CONF_CMDSTAT_CAPS) {
+ data = pcie_conf_read(bdf, PCIE_CONF_CAPPTR);
+ reg = PCIE_CONF_CAPPTR_FIRST(data);
+ }
+
+ while (reg) {
+ data = pcie_conf_read(bdf, reg);
+
+ if (PCIE_CONF_CAP_ID(data) == cap_id) {
+ break;
+ }
+
+ reg = PCIE_CONF_CAP_NEXT(data);
+ }
+
+ return reg;
+}
+
bool pcie_get_mbar(pcie_bdf_t bdf, unsigned int index, struct pcie_mbar *mbar)
{
uintptr_t phys_addr;
diff --git a/include/drivers/pcie/msi.h b/include/drivers/pcie/msi.h
index 865df77..a24feeb 100644
--- a/include/drivers/pcie/msi.h
+++ b/include/drivers/pcie/msi.h
@@ -16,34 +16,6 @@
#endif
/**
- * @brief Find a PCI(e) capability in an endpoint's configuration space.
- *
- * @param bdf the PCI endpoint to examine
- * @param cap_id the capability ID of interest
- * @return the index of the configuration word, or 0 if no capability.
- *
- * Note: PCI(e) capabilities are only used in the MSI code, so for
- * now, capabilities-related code is only included when MSI is. It
- * can easily be separated out if/when its use spreads.
- */
-extern uint32_t pcie_get_cap(pcie_bdf_t bdf, uint32_t cap_id);
-
-/*
- * Configuration word 13 contains the head of the capabilities list.
- */
-
-#define PCIE_CONF_CAPPTR 13U /* capabilities pointer */
-#define PCIE_CONF_CAPPTR_FIRST(w) (((w) >> 2) & 0x3FU)
-
-/*
- * The first word of every capability contains a capability identifier,
- * and a link to the next capability (or 0) in configuration space.
- */
-
-#define PCIE_CONF_CAP_ID(w) ((w) & 0xFFU)
-#define PCIE_CONF_CAP_NEXT(w) (((w) >> 10) & 0x3FU)
-
-/**
* @brief Compute the target address for an MSI posted write.
*
* This function is exported by the arch, board or SoC code.
diff --git a/include/drivers/pcie/pcie.h b/include/drivers/pcie/pcie.h
index cff6053..c5b5525 100644
--- a/include/drivers/pcie/pcie.h
+++ b/include/drivers/pcie/pcie.h
@@ -136,6 +136,30 @@
*/
extern void pcie_irq_enable(pcie_bdf_t bdf, unsigned int irq);
+/**
+ * @brief Find a PCI(e) capability in an endpoint's configuration space.
+ *
+ * @param bdf the PCI endpoint to examine
+ * @param cap_id the capability ID of interest
+ * @return the index of the configuration word, or 0 if no capability.
+ */
+extern uint32_t pcie_get_cap(pcie_bdf_t bdf, uint32_t cap_id);
+
+/*
+ * Configuration word 13 contains the head of the capabilities list.
+ */
+
+#define PCIE_CONF_CAPPTR 13U /* capabilities pointer */
+#define PCIE_CONF_CAPPTR_FIRST(w) (((w) >> 2) & 0x3FU)
+
+/*
+ * The first word of every capability contains a capability identifier,
+ * and a link to the next capability (or 0) in configuration space.
+ */
+
+#define PCIE_CONF_CAP_ID(w) ((w) & 0xFFU)
+#define PCIE_CONF_CAP_NEXT(w) (((w) >> 10) & 0x3FU)
+
/*
* Configuration word 0 aligns directly with pcie_id_t.
*/
