dts: arm: microchip: pic32cx_sg: Add pincontrol nodes
Adds the pinctrl node and encapsulates the port nodes within
the pinctrl node for pic32cx sg series of socs.
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
diff --git a/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg.dtsi b/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg.dtsi
index 4131f97..67a61c1 100644
--- a/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg.dtsi
+++ b/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg.dtsi
@@ -38,22 +38,29 @@
reg = <0x20000000 DT_SIZE_K(256)>;
};
- porta: gpio@41008000 {
- status = "disabled";
- compatible = "microchip,port-g1-gpio";
- reg = <0x41008000 0x80>;
- gpio-controller;
- #gpio-cells = <2>;
- #microchip,pin-cells = <2>;
- };
+ pinctrl: pinctrl@41008000 {
+ compatible = "microchip,port-g1-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x41008000 0x41008000 0x200>;
- portb: gpio@41008080 {
- status = "disabled";
- compatible = "microchip,port-g1-gpio";
- reg = <0x41008080 0x80>;
- gpio-controller;
- #gpio-cells = <2>;
- #microchip,pin-cells = <2>;
+ porta: gpio@41008000 {
+ compatible = "microchip,port-g1-gpio";
+ reg = <0x41008000 0x80>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #microchip,pin-cells = <2>;
+ status = "disabled";
+ };
+
+ portb: gpio@41008080 {
+ compatible = "microchip,port-g1-gpio";
+ reg = <0x41008080 0x80>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #microchip,pin-cells = <2>;
+ status = "disabled";
+ };
};
};
};
diff --git a/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_100.dtsi b/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_100.dtsi
index 58ad9b7..b384b98 100644
--- a/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_100.dtsi
+++ b/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_100.dtsi
@@ -8,15 +8,13 @@
#include <microchip/pic32c/pic32cx_sg/common/pic32cx_sg.dtsi>
-/ {
- soc {
- portc: gpio@41008100 {
- status = "disabled";
- compatible = "microchip,port-g1-gpio";
- reg = <0x41008100 0x80>;
- gpio-controller;
- #gpio-cells = <2>;
- #microchip,pin-cells = <2>;
- };
+&pinctrl {
+ portc: gpio@41008100 {
+ compatible = "microchip,port-g1-gpio";
+ reg = <0x41008100 0x80>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #microchip,pin-cells = <2>;
+ status = "disabled";
};
};
diff --git a/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_128.dtsi b/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_128.dtsi
index f64879f..a766a6e 100644
--- a/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_128.dtsi
+++ b/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_128.dtsi
@@ -8,24 +8,22 @@
#include <microchip/pic32c/pic32cx_sg/common/pic32cx_sg.dtsi>
-/ {
- soc {
- portc: gpio@41008100 {
- status = "disabled";
- compatible = "microchip,port-g1-gpio";
- reg = <0x41008100 0x80>;
- gpio-controller;
- #gpio-cells = <2>;
- #microchip,pin-cells = <2>;
- };
+&pinctrl {
+ portc: gpio@41008100 {
+ compatible = "microchip,port-g1-gpio";
+ reg = <0x41008100 0x80>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #microchip,pin-cells = <2>;
+ status = "disabled";
+ };
- portd: gpio@41008180 {
- status = "disabled";
- compatible = "microchip,port-g1-gpio";
- reg = <0x41008180 0x80>;
- gpio-controller;
- #gpio-cells = <2>;
- #microchip,pin-cells = <2>;
- };
+ portd: gpio@41008180 {
+ compatible = "microchip,port-g1-gpio";
+ reg = <0x41008180 0x80>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #microchip,pin-cells = <2>;
+ status = "disabled";
};
};
diff --git a/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_80.dtsi b/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_80.dtsi
index 979b221..ffa788f 100644
--- a/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_80.dtsi
+++ b/dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_80.dtsi
@@ -8,15 +8,13 @@
#include <microchip/pic32c/pic32cx_sg/common/pic32cx_sg.dtsi>
-/ {
- soc {
- portc: gpio@41008100 {
- status = "disabled";
- compatible = "microchip,port-g1-gpio";
- reg = <0x41008100 0x80>;
- gpio-controller;
- #gpio-cells = <2>;
- #microchip,pin-cells = <2>;
- };
+&pinctrl {
+ portc: gpio@41008100 {
+ compatible = "microchip,port-g1-gpio";
+ reg = <0x41008100 0x80>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #microchip,pin-cells = <2>;
+ status = "disabled";
};
};
