dts: arm: st: mp13: stm32mp13 new series with cortex A7
Put the flash in DDR 0xC0000000
Put the SRAM in DDR 0xD0000000
Signed-off-by: Julien Racki <julien.racki@st.com>
diff --git a/dts/arm/st/mp13/stm32mp13.dtsi b/dts/arm/st/mp13/stm32mp13.dtsi
new file mode 100644
index 0000000..d781890
--- /dev/null
+++ b/dts/arm/st/mp13/stm32mp13.dtsi
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-a.dtsi>
+
+#include <freq.h>
+#include <mem.h>
+
+#include <zephyr/dt-bindings/clock/stm32mp13_clock.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <zephyr/dt-bindings/reset/stm32mp13_reset.h>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ soc {
+ interrupt-parent = <&gic>;
+
+ sysram: memory@2ffe0000 {
+ compatible = "mmio-sram";
+ reg = <0x2FFE0000 DT_SIZE_K(128)>;
+ };
+
+ uart4: serial@40010000 {
+ compatible = "st,stm32-uart";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc STM32_CLOCK(APB1, 16)>;
+ resets = <&rctl STM32_RESET(APB1, 16)>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ status = "disabled";
+ };
+
+ rcc: rcc@50000000 {
+ compatible = "st,stm32-rcc";
+ reg = <0x50000000 0x1000>;
+ #clock-cells = <2>;
+
+ rctl: reset-controller {
+ compatible = "st,stm32-rcc-rctl";
+ #reset-cells = <1>;
+ set-bit-to-deassert;
+ };
+ };
+
+ pinctrl: pin-controller@50002000 {
+ compatible = "st,stm32-pinctrl";
+ reg = <0x50002000 0x9000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpioa: gpio@50002000 {
+ compatible = "st,stm32-gpio";
+ reg = <0x50002000 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&rcc STM32_CLOCK(AHB4, 0)>;
+ };
+
+ gpiob: gpio@50003000 {
+ compatible = "st,stm32-gpio";
+ reg = <0x50003000 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&rcc STM32_CLOCK(AHB4, 1)>;
+ };
+
+ gpioc: gpio@50004000 {
+ compatible = "st,stm32-gpio";
+ reg = <0x50004000 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&rcc STM32_CLOCK(AHB4, 2)>;
+ };
+
+ gpiod: gpio@50005000 {
+ compatible = "st,stm32-gpio";
+ reg = <0x50005000 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&rcc STM32_CLOCK(AHB4, 3)>;
+ };
+
+ gpioe: gpio@50006000 {
+ compatible = "st,stm32-gpio";
+ reg = <0x50006000 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&rcc STM32_CLOCK(AHB4, 4)>;
+ };
+
+ gpiof: gpio@50007000 {
+ compatible = "st,stm32-gpio";
+ reg = <0x50007000 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&rcc STM32_CLOCK(AHB4, 5)>;
+ };
+
+ gpiog: gpio@50008000 {
+ compatible = "st,stm32-gpio";
+ reg = <0x50008000 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&rcc STM32_CLOCK(AHB4, 6)>;
+ };
+
+ gpioh: gpio@50009000 {
+ compatible = "st,stm32-gpio";
+ reg = <0x50009000 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&rcc STM32_CLOCK(AHB4, 7)>;
+ };
+
+ gpioi: gpio@5000a000 {
+ compatible = "st,stm32-gpio";
+ reg = <0x5000a000 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&rcc STM32_CLOCK(AHB4, 8)>;
+ };
+ };
+
+ exti: interrupt-controller@5000d000 {
+ compatible = "st,stm32g0-exti","st,stm32-exti";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ reg = <0x5000D000 0x400>;
+ num-lines = <16>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 66 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ interrupt-names = "line0", "line1", "line2", "line3",
+ "line4", "line5", "line6", "line7",
+ "line8", "line9", "line10", "line11",
+ "line12", "line13", "line14", "line15";
+ line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
+ <4 1>, <5 1>, <6 1>, <7 1>,
+ <8 1>, <9 1>, <10 1>, <11 1>,
+ <12 1>, <13 1>, <14 1>, <15 1>;
+ };
+ };
+
+ gic: gic@A0021000 {
+ compatible = "arm,gic-v2", "arm,gic";
+ reg = <0xA0021000 0x1000>,
+ <0xA0022000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ status = "okay";
+ };
+
+ ddr_code: memory@C0000000 {
+ compatible = "mmio-sram";
+ reg = <0xC0000000 0x10000000>;
+ };
+
+ ddr_data: memory@D0000000 {
+ compatible = "mmio-sram";
+ reg = <0xD0000000 0x10000000>;
+ };
+
+ clocks {
+
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ status = "disabled";
+ };
+
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ status = "disabled";
+ };
+
+ cpusw: cpusw {
+ #clock-cells = <0>;
+ compatible = "st,stm32mp13-cpu-clock-mux";
+ status = "disabled";
+ };
+
+ pll1: pll: pll {
+ #clock-cells = <0>;
+ compatible = "st,stm32mp13-pll-clock";
+ status = "disabled";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+ };
+};
diff --git a/dts/arm/st/mp13/stm32mp135.dtsi b/dts/arm/st/mp13/stm32mp135.dtsi
new file mode 100644
index 0000000..4b754a6
--- /dev/null
+++ b/dts/arm/st/mp13/stm32mp135.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/mp13/stm32mp13.dtsi>
+
+/ {
+ soc {
+ compatible = "st,stm32mp135", "st,stm32mp13", "simple-bus";
+ };
+};
