dts: arm: st: stm32mp1: remove U suffix from "resets" in DTSI
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
diff --git a/dts/arm/st/mp1/stm32mp157.dtsi b/dts/arm/st/mp1/stm32mp157.dtsi
index eda7922..39f6044 100644
--- a/dts/arm/st/mp1/stm32mp157.dtsi
+++ b/dts/arm/st/mp1/stm32mp157.dtsi
@@ -270,7 +270,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x4000e000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 14)>;
- resets = <&rctl STM32_RESET(APB1, 14U)>;
+ resets = <&rctl STM32_RESET(APB1, 14)>;
interrupts = <38 0>;
status = "disabled";
};
@@ -279,7 +279,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x4000f000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 15)>;
- resets = <&rctl STM32_RESET(APB1, 15U)>;
+ resets = <&rctl STM32_RESET(APB1, 15)>;
interrupts = <39 0>;
status = "disabled";
};
@@ -288,7 +288,7 @@
compatible = "st,stm32-uart";
reg = <0x40010000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 16)>;
- resets = <&rctl STM32_RESET(APB1, 16U)>;
+ resets = <&rctl STM32_RESET(APB1, 16)>;
interrupts = <52 0>;
status = "disabled";
};
@@ -297,7 +297,7 @@
compatible = "st,stm32-uart";
reg = <0x40011000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
- resets = <&rctl STM32_RESET(APB1, 17U)>;
+ resets = <&rctl STM32_RESET(APB1, 17)>;
interrupts = <53 0>;
status = "disabled";
};
@@ -306,7 +306,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x44003000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 13)>;
- resets = <&rctl STM32_RESET(APB2, 13U)>;
+ resets = <&rctl STM32_RESET(APB2, 13)>;
interrupts = <71 0>;
status = "disabled";
};
@@ -315,7 +315,7 @@
compatible = "st,stm32-uart";
reg = <0x40018000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1, 18U)>;
+ resets = <&rctl STM32_RESET(APB1, 18)>;
interrupts = <82 0>;
status = "disabled";
};
@@ -324,7 +324,7 @@
compatible = "st,stm32-uart";
reg = <0x40019000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1, 19U)>;
+ resets = <&rctl STM32_RESET(APB1, 19)>;
interrupts = <83 0>;
status = "disabled";
};
@@ -345,7 +345,7 @@
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>;
- resets = <&rctl STM32_RESET(APB1, 1U)>;
+ resets = <&rctl STM32_RESET(APB1, 1)>;
interrupts = <29 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -367,7 +367,7 @@
compatible = "st,stm32-timers";
reg = <0x40003000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 3)>;
- resets = <&rctl STM32_RESET(APB1, 3U)>;
+ resets = <&rctl STM32_RESET(APB1, 3)>;
interrupts = <50 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -400,7 +400,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK(APB4, 0)>;
- resets = <&rctl STM32_RESET(APB4, 26U)>;
+ resets = <&rctl STM32_RESET(APB4, 26)>;
status = "disabled";
};
};
