| commit | 7a276208aa499136741f87dee6cabf12f5bfae8e | [log] [tgz] |
|---|---|---|
| author | Robert Hancock <robert.hancock@calian.com> | Mon Feb 10 15:19:17 2025 -0600 |
| committer | Benjamin Cabé <kartben@gmail.com> | Mon Mar 17 02:20:50 2025 +0100 |
| tree | 5e990acd026f973572f0f9c5b7b98a323d7ef8b1 | |
| parent | e36d4fafd2bea17aa10f79fff059955787496190 [diff] |
soc: xlnx: zynqmp: Enable I/D caches On ZynqMP, the RPU Cortex-R5 cores come up by default without instruction and data caches enabled. Enable them as part of soc_early_init_hook when CONFIG_CACHE_MANAGEMENT is enabled. Signed-off-by: Robert Hancock <robert.hancock@calian.com>