tests: clock_control: stm32_common: Add a comment when enabling adc node
On some tests adc node is enabled w/o setting any domain clock.
This is made on purpose but deserves a comment to avoid surprises
for the reader.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay
index 610cd80..cff0687 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay
@@ -70,5 +70,6 @@
};
&adc1 {
+ /* Basic test only. Don't configure domain clock. */
status = "okay";
};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay
index 610cd80..cff0687 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay
@@ -70,5 +70,6 @@
};
&adc1 {
+ /* Basic test only. Don't configure domain clock. */
status = "okay";
};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay
index 46aa06b..98fbe97 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay
@@ -77,5 +77,6 @@
};
&adc1 {
+ /* Basic test only. Don't configure domain clock. */
status = "okay";
};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_hsi_lptim1_lse.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_hsi_lptim1_lse.overlay
index 17224fd..a95e7ee 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_hsi_lptim1_lse.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_hsi_lptim1_lse.overlay
@@ -83,5 +83,6 @@
};
&adc1 {
+ /* Basic test only. Don't configure domain clock. */
status = "okay";
};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_sysclk_lptim1_lsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_sysclk_lptim1_lsi.overlay
index 66f28d5..09e0d08 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_sysclk_lptim1_lsi.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_sysclk_lptim1_lsi.overlay
@@ -83,5 +83,6 @@
};
&adc1 {
+ /* Basic test only. Don't configure domain clock. */
status = "okay";
};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_hsi_lptim1_lse.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_hsi_lptim1_lse.overlay
index e28c47c..e596c6e 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_hsi_lptim1_lse.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_hsi_lptim1_lse.overlay
@@ -83,5 +83,6 @@
};
&adc1 {
+ /* Basic test only. Don't configure domain clock. */
status = "okay";
};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_sysclk_lptim1_lsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_sysclk_lptim1_lsi.overlay
index a460261..9ec7434 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_sysclk_lptim1_lsi.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_sysclk_lptim1_lsi.overlay
@@ -77,5 +77,6 @@
};
&adc1 {
+ /* Basic test only. Don't configure domain clock. */
status = "okay";
};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_sysclk_lptim1_lsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_sysclk_lptim1_lsi.overlay
index 6e00ee8..4775abe 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_sysclk_lptim1_lsi.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_sysclk_lptim1_lsi.overlay
@@ -82,5 +82,6 @@
};
&adc1 {
+ /* Basic test only. Don't configure domain clock. */
status = "okay";
};
